ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,

[karo-tx-uboot.git] / cpu / ppc4xx / cpu_init.c

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index e2d04027815a8e44b430ce2f17764ad78bb8ddd7..281819af602db1df0fd816b18dc193f55cee4079 100644 (file)
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -138,7 +138,9 @@ void reconfigure_pll(u32 new_cpu_freq)
 void
 cpu_init_f (void)
 {
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX)   || \
+    defined(CONFIG_460GT) || defined(CONFIG_460SX)
        u32 val;
 #endif
 
@@ -301,6 +303,18 @@ cpu_init_f (void)
        val |= 0x400;
        mtsdr(SDR0_USB2HOST_CFG, val);
 #endif /* CONFIG_460EX */
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
+    defined(CONFIG_405EX) || defined(CONFIG_460SX)
+       /*
+        * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
+        */
+       val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+       mtdcr(plb0_acr, val);
+       val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+       mtdcr(plb1_acr, val);
+#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }
 
 /*