sf: Add dual memories support - DUAL_PARALLEL

[karo-tx-uboot.git] / doc / SPI / README.dual-flash

diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
index ba0aa265e0177a393fd3926cc91452acb1777686..6c88d65dd49f86a8e1edcf30d4b5b4ccdc53d0d7 100644 (file)
--- a/doc/SPI/README.dual-flash
+++ b/doc/SPI/README.dual-flash
@@ -54,6 +54,33 @@ SF_DUAL_STACKED_FLASH:
                by default, if U_PAGE is unset lower memory should accessible,
                once user wants to access upper memory need to set U_PAGE.
 
+SPI_FLASH_CONN_DUALPARALLEL:
+       - dual spi/qspi flash memories are connected with a single chipselect
+         line and these two memories are operating parallel with separate buses.
+       - xilinx zynq qspi controller has implemented this feature [1]
+
+  +-------------+           CS         +---------------+
+  |            |---------------------->|               |
+  |            |        I0[3:0]        | Upper Flash   |
+  |            |<=====================>| memory        |
+  |            |          CLK          | (SPI/QSPI)    |
+  |            |---------------------->|               |
+  | Controller |           CS          +---------------+
+  | SPI/QSPI   |---------------------->|               |
+  |            |        I0[3:0]        | Lower Flash   |
+  |            |<=====================>| memory        |
+  |            |          CLK          | (SPI/QSPI)    |
+  |            |---------------------->|               |
+  +-------------+                      +---------------+
+
+       - two memory flash devices should has same hw part attributes (like size,
+         vendor..etc)
+       - Configurations:
+               Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
+       - Operation:
+               Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
+               and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
+
 Note: Technically there is only one CS line from the controller, but
 zynq qspi controller has an internal hw logic to enable additional CS
 when controller is configured for dual memories.