drm: remove a bunch of typedefs on the userspace interface

[karo-tx-linux.git] / drivers / char / drm / radeon_cp.c

diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index c1850ecac302cdbb3ae0089ff778a14befadc0dc..cfc5aa16de224c02a718f1f7b25bc202aca4ba03 100644 (file)
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -830,6 +830,15 @@ static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
        return RADEON_READ(RADEON_PCIE_DATA);
 }
 
+static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
+{
+       u32 ret;
+       RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
+       ret = RADEON_READ(RADEON_IGPGART_DATA);
+       RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
+       return ret;
+}
+
 #if RADEON_FIFO_DEBUG
 static void radeon_status(drm_radeon_private_t * dev_priv)
 {
@@ -1267,7 +1276,44 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
        }
 }
 
-/* Enable or disable PCI-E GART on the chip */
+/* Enable or disable IGP GART on the chip */
+static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+{
+       u32 temp, tmp;
+
+       tmp = RADEON_READ(RADEON_AIC_CNTL);
+       if (on) {
+               DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
+                        dev_priv->gart_vm_start,
+                        (long)dev_priv->gart_info.bus_addr,
+                        dev_priv->gart_size);
+
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
+                                    dev_priv->gart_info.bus_addr);
+
+               temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
+
+               RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
+               dev_priv->gart_size = 32*1024*1024;
+               RADEON_WRITE(RADEON_MC_AGP_LOCATION,
+                            (((dev_priv->gart_vm_start - 1 +
+                              dev_priv->gart_size) & 0xffff0000) |
+                            (dev_priv->gart_vm_start >> 16)));
+
+               temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
+
+               RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
+               RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
+               RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
+       }
+}
+
 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 {
        u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
@@ -1302,6 +1348,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 {
        u32 tmp;
 
+       if (dev_priv->flags & RADEON_IS_IGPGART) {
+               radeon_set_igpgart(dev_priv, on);
+               return;
+       }
+
        if (dev_priv->flags & RADEON_IS_PCIE) {
                radeon_set_pciegart(dev_priv, on);
                return;
@@ -1369,6 +1420,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
                return DRM_ERR(EINVAL);
        }
 
+       /* Enable vblank on CRTC1 for older X servers
+        */
+       dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
+
        switch(init->func) {
        case RADEON_INIT_R200_CP:
                dev_priv->microcode_version = UCODE_R200;
@@ -1450,13 +1505,13 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
                                         RADEON_ROUND_MODE_TRUNC |
                                         RADEON_ROUND_PREC_8TH_PIX);
 
-       DRM_GETSAREA();
 
        dev_priv->ring_offset = init->ring_offset;
        dev_priv->ring_rptr_offset = init->ring_rptr_offset;
        dev_priv->buffers_offset = init->buffers_offset;
        dev_priv->gart_textures_offset = init->gart_textures_offset;
 
+       dev_priv->sarea = drm_getsarea(dev);
        if (!dev_priv->sarea) {
                DRM_ERROR("could not find sarea!\n");
                radeon_do_cleanup_cp(dev);
@@ -1620,20 +1675,22 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 #endif
        {
                /* if we have an offset set from userspace */
-               if (dev_priv->pcigart_offset) {
+               if (dev_priv->pcigart_offset_set) {
                        dev_priv->gart_info.bus_addr =
                            dev_priv->pcigart_offset + dev_priv->fb_location;
                        dev_priv->gart_info.mapping.offset =
                            dev_priv->gart_info.bus_addr;
                        dev_priv->gart_info.mapping.size =
-                           RADEON_PCIGART_TABLE_SIZE;
+                           dev_priv->gart_info.table_size;
 
                        drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
                        dev_priv->gart_info.addr =
                            dev_priv->gart_info.mapping.handle;
 
-                       dev_priv->gart_info.is_pcie =
-                           !!(dev_priv->flags & RADEON_IS_PCIE);
+                       if (dev_priv->flags & RADEON_IS_PCIE)
+                               dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
+                       else
+                               dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
                        dev_priv->gart_info.gart_table_location =
                            DRM_ATI_GART_FB;
 
@@ -1641,6 +1698,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
                                  dev_priv->gart_info.addr,
                                  dev_priv->pcigart_offset);
                } else {
+                       if (dev_priv->flags & RADEON_IS_IGPGART)
+                               dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
+                       else
+                               dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
                        dev_priv->gart_info.gart_table_location =
                            DRM_ATI_GART_MAIN;
                        dev_priv->gart_info.addr = NULL;
@@ -1714,7 +1775,7 @@ static int radeon_do_cleanup_cp(drm_device_t * dev)
                if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
                {
                        drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
-                       dev_priv->gart_info.addr = NULL;
+                       dev_priv->gart_info.addr = 0;
                }
        }
        /* only clear to the start of flags */
@@ -2110,7 +2171,7 @@ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
 }
 
 static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
-                                drm_dma_t * d)
+                                struct drm_dma * d)
 {
        int i;
        drm_buf_t *buf;
@@ -2139,8 +2200,8 @@ int radeon_cp_buffers(DRM_IOCTL_ARGS)
        DRM_DEVICE;
        drm_device_dma_t *dma = dev->dma;
        int ret = 0;
-       drm_dma_t __user *argp = (void __user *)data;
-       drm_dma_t d;
+       struct drm_dma __user *argp = (void __user *)data;
+       struct drm_dma d;
 
        LOCK_TEST_WITH_RETURN(dev, filp);
 
@@ -2222,6 +2283,8 @@ int radeon_driver_firstopen(struct drm_device *dev)
        drm_local_map_t *map;
        drm_radeon_private_t *dev_priv = dev->dev_private;
 
+       dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
+
        ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
                         drm_get_resource_len(dev, 2), _DRM_REGISTERS,
                         _DRM_READ_ONLY, &dev_priv->mmio);