Merge tag 'clk-hisi' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1...

[karo-tx-linux.git] / drivers / clk / hisilicon / clk-hi3620.c

diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index 38faa469d2883591cdaa7f863d5d6a569af8b5ab..233eba22187a900baf7427f51f5ab7820811e4ed 100644 (file)
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -210,34 +210,25 @@ static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = {
 
 static void __init hi3620_clk_init(struct device_node *np)
 {
-       void __iomem *base;
+       struct hisi_clock_data *clk_data;
 
-       if (np) {
-               base = of_iomap(np, 0);
-               if (!base) {
-                       pr_err("failed to map Hi3620 clock registers\n");
-                       return;
-               }
-       } else {
-               pr_err("failed to find Hi3620 clock node in DTS\n");
+       clk_data = hisi_clk_init(np, HI3620_NR_CLKS);
+       if (!clk_data)
                return;
-       }
-
-       hisi_clk_init(np, HI3620_NR_CLKS);
 
        hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
                                     ARRAY_SIZE(hi3620_fixed_rate_clks),
-                                    base);
+                                    clk_data);
        hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
                                       ARRAY_SIZE(hi3620_fixed_factor_clks),
-                                      base);
+                                      clk_data);
        hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
-                             base);
+                             clk_data);
        hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
-                                 base);
+                                 clk_data);
        hisi_clk_register_gate_sep(hi3620_seperated_gate_clks,
                                   ARRAY_SIZE(hi3620_seperated_gate_clks),
-                                  base);
+                                  clk_data);
 }
 CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);