gpio/langwell: re-read the IRQ status register after each iteration

[karo-tx-linux.git] / drivers / gpio / gpio-langwell.c

diff --git a/drivers/gpio/gpio-langwell.c b/drivers/gpio/gpio-langwell.c
index 00692e89ef878ac20834354df75f173d40fe68b8..a1c8754f52cf1b523c3da1bb9e572dc084ddde0b 100644 (file)
--- a/drivers/gpio/gpio-langwell.c
+++ b/drivers/gpio/gpio-langwell.c
@@ -36,6 +36,7 @@
 #include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
+#include <linux/irqdomain.h>
 
 /*
  * Langwell chip has 64 pins and thus there are 2 32bit registers to control
@@ -66,8 +67,8 @@ struct lnw_gpio {
        struct gpio_chip                chip;
        void                            *reg_base;
        spinlock_t                      lock;
-       unsigned                        irq_base;
        struct pci_dev                  *pdev;
+       struct irq_domain               *domain;
 };
 
 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
@@ -176,13 +177,13 @@ static int lnw_gpio_direction_output(struct gpio_chip *chip,
 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
        struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
-       return lnw->irq_base + offset;
+       return irq_create_mapping(lnw->domain, offset);
 }
 
 static int lnw_irq_type(struct irq_data *d, unsigned type)
 {
        struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
-       u32 gpio = d->irq - lnw->irq_base;
+       u32 gpio = irqd_to_hwirq(d);
        unsigned long flags;
        u32 value;
        void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
@@ -249,20 +250,55 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
        /* check GPIO controller to check which pin triggered the interrupt */
        for (base = 0; base < lnw->chip.ngpio; base += 32) {
                gedr = gpio_reg(&lnw->chip, base, GEDR);
-               pending = readl(gedr);
-               while (pending) {
+               while ((pending = readl(gedr))) {
                        gpio = __ffs(pending);
                        mask = BIT(gpio);
-                       pending &= ~mask;
                        /* Clear before handling so we can't lose an edge */
                        writel(mask, gedr);
-                       generic_handle_irq(lnw->irq_base + base + gpio);
+                       generic_handle_irq(irq_find_mapping(lnw->domain,
+                                                           base + gpio));
                }
        }
 
        chip->irq_eoi(data);
 }
 
+static void lnw_irq_init_hw(struct lnw_gpio *lnw)
+{
+       void __iomem *reg;
+       unsigned base;
+
+       for (base = 0; base < lnw->chip.ngpio; base += 32) {
+               /* Clear the rising-edge detect register */
+               reg = gpio_reg(&lnw->chip, base, GRER);
+               writel(0, reg);
+               /* Clear the falling-edge detect register */
+               reg = gpio_reg(&lnw->chip, base, GFER);
+               writel(0, reg);
+               /* Clear the edge detect status register */
+               reg = gpio_reg(&lnw->chip, base, GEDR);
+               writel(~0, reg);
+       }
+}
+
+static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
+                           irq_hw_number_t hw)
+{
+       struct lnw_gpio *lnw = d->host_data;
+
+       irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
+                                     "demux");
+       irq_set_chip_data(virq, lnw);
+       irq_set_irq_type(virq, IRQ_TYPE_NONE);
+
+       return 0;
+}
+
+static const struct irq_domain_ops lnw_gpio_irq_ops = {
+       .map = lnw_gpio_irq_map,
+       .xlate = irq_domain_xlate_twocell,
+};
+
 #ifdef CONFIG_PM
 static int lnw_gpio_runtime_resume(struct device *dev)
 {
@@ -300,23 +336,22 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
                        const struct pci_device_id *id)
 {
        void *base;
-       int i;
        resource_size_t start, len;
        struct lnw_gpio *lnw;
-       u32 irq_base;
        u32 gpio_base;
        int retval = 0;
+       int ngpio = id->driver_data;
 
        retval = pci_enable_device(pdev);
        if (retval)
-               goto done;
+               return retval;
 
        retval = pci_request_regions(pdev, "langwell_gpio");
        if (retval) {
                dev_err(&pdev->dev, "error requesting resources\n");
                goto err2;
        }
-       /* get the irq_base from bar1 */
+       /* get the gpio_base from bar1 */
        start = pci_resource_start(pdev, 1);
        len = pci_resource_len(pdev, 1);
        base = ioremap_nocache(start, len);
@@ -324,28 +359,32 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
                dev_err(&pdev->dev, "error mapping bar1\n");
                goto err3;
        }
-       irq_base = *(u32 *)base;
        gpio_base = *((u32 *)base + 1);
        /* release the IO mapping, since we already get the info from bar1 */
        iounmap(base);
        /* get the register base from bar0 */
        start = pci_resource_start(pdev, 0);
        len = pci_resource_len(pdev, 0);
-       base = ioremap_nocache(start, len);
+       base = devm_ioremap_nocache(&pdev->dev, start, len);
        if (!base) {
                dev_err(&pdev->dev, "error mapping bar0\n");
                retval = -EFAULT;
                goto err3;
        }
 
-       lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
+       lnw = devm_kzalloc(&pdev->dev, sizeof(struct lnw_gpio), GFP_KERNEL);
        if (!lnw) {
                dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
                retval = -ENOMEM;
-               goto err4;
+               goto err3;
        }
+
+       lnw->domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
+                                           &lnw_gpio_irq_ops, lnw);
+       if (!lnw->domain)
+               goto err3;
+
        lnw->reg_base = base;
-       lnw->irq_base = irq_base;
        lnw->chip.label = dev_name(&pdev->dev);
        lnw->chip.request = lnw_gpio_request;
        lnw->chip.direction_input = lnw_gpio_direction_input;
@@ -354,38 +393,32 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
        lnw->chip.set = lnw_gpio_set;
        lnw->chip.to_irq = lnw_gpio_to_irq;
        lnw->chip.base = gpio_base;
-       lnw->chip.ngpio = id->driver_data;
+       lnw->chip.ngpio = ngpio;
        lnw->chip.can_sleep = 0;
        lnw->pdev = pdev;
        pci_set_drvdata(pdev, lnw);
        retval = gpiochip_add(&lnw->chip);
        if (retval) {
                dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
-               goto err5;
+               goto err3;
        }
+
+       lnw_irq_init_hw(lnw);
+
        irq_set_handler_data(pdev->irq, lnw);
        irq_set_chained_handler(pdev->irq, lnw_irq_handler);
-       for (i = 0; i < lnw->chip.ngpio; i++) {
-               irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
-                                             handle_simple_irq, "demux");
-               irq_set_chip_data(i + lnw->irq_base, lnw);
-       }
 
        spin_lock_init(&lnw->lock);
 
        pm_runtime_put_noidle(&pdev->dev);
        pm_runtime_allow(&pdev->dev);
 
-       goto done;
-err5:
-       kfree(lnw);
-err4:
-       iounmap(base);
+       return 0;
+
 err3:
        pci_release_regions(pdev);
 err2:
        pci_disable_device(pdev);
-done:
        return retval;
 }