#ifndef CONFIG_MPC512X
#include <asm/arch/imx-regs.h>
#endif
+#if defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)
+#include <asm/arch/clock.h>
+#endif
/* FSL IIM-specific constants */
#define STAT_BUSY 0x80
u32 sdat;
u32 prev;
u32 srev;
- u32 prg_p;
+ u32 preg_p;
u32 scs[0x1f5];
struct {
u32 word[0x100];
} bank[8];
};
+#if !defined(CONFIG_SOC_MX51) && !defined(CONFIG_SOC_MX53)
+#define enable_efuse_prog_supply(enable)
+#endif
+
static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
const char *caller)
{
iim_write32(®s->ua, bank << 3 | word >> 5);
iim_write32(®s->la, (word << 3 | bit) & 0xff);
if (fctl == FCTL_PRG)
- iim_write32(®s->prg_p, 0xaa);
+ iim_write32(®s->preg_p, 0xaa);
iim_setbits32(®s->fctl, fctl);
while (iim_read32(®s->stat) & STAT_BUSY)
udelay(20);
clear_status(regs);
direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
- iim_write32(®s->prg_p, 0x00);
+ iim_write32(®s->preg_p, 0x00);
if (err & ERR_PRGE) {
puts("fsl_iim fuse_prog(): Program error\n");
if (ret)
return ret;
+ enable_efuse_prog_supply(1);
for (bit = 0; val; bit++, val >>= 1)
if (val & 0x01) {
ret = prog_bit(regs, bank, word, bit);
- if (ret)
+ if (ret) {
+ enable_efuse_prog_supply(0);
return ret;
+ }
}
+ enable_efuse_prog_supply(0);
return 0;
}