uint fevt; /* Force event register */
uint admaes; /* ADMA error status register */
uint adsaddr; /* ADMA system address register */
- char reserved2[160]; /* reserved */
+ char reserved2[100]; /* reserved */
+ uint vendorspec; /* Vendor Specific register */
+ char reserved3[56]; /* reserved */
uint hostver; /* Host controller version register */
- char reserved3[4]; /* reserved */
- uint dmaerraddr; /* DMA error address register */
char reserved4[4]; /* reserved */
- uint dmaerrattr; /* DMA error attribute register */
+ uint dmaerraddr; /* DMA error address register */
char reserved5[4]; /* reserved */
+ uint dmaerrattr; /* DMA error attribute register */
+ char reserved6[4]; /* reserved */
uint hostcapblt2; /* Host controller capabilities register 2 */
- char reserved6[8]; /* reserved */
+ char reserved7[8]; /* reserved */
uint tcr; /* Tuning control register */
- char reserved7[28]; /* reserved */
+ char reserved8[28]; /* reserved */
uint sddirctl; /* SD direction control register */
- char reserved8[712]; /* reserved */
+ char reserved9[712]; /* reserved */
uint scr; /* eSDHC control register */
};
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_SOC_LS102XA)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
uint blocks;
char *buffer;
uint databuf;
uint size;
- uint irqstat;
uint timeout;
+ int wml = esdhc_read32(®s->wml);
if (data->flags & MMC_DATA_READ) {
+ wml &= WML_RD_WML_MASK;
blocks = data->blocks;
buffer = data->dest;
while (blocks) {
timeout = PIO_TIMEOUT;
size = data->blocksize;
- irqstat = esdhc_read32(®s->irqstat);
- while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
- && --timeout);
- if (timeout <= 0) {
- printf("\nData Read Failed in PIO Mode.");
- return;
- }
- while (size && (!(irqstat & IRQSTAT_TC))) {
- udelay(100); /* Wait before last byte transfer complete */
- irqstat = esdhc_read32(®s->irqstat);
- databuf = in_le32(®s->datport);
- *((uint *)buffer) = databuf;
- buffer += 4;
- size -= 4;
+ while (size &&
+ !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
+ int i;
+ u32 prsstat;
+
+ while (!((prsstat = esdhc_read32(®s->prsstat)) &
+ PRSSTAT_BREN) && --timeout)
+ /* NOP */;
+ if (!(prsstat & PRSSTAT_BREN)) {
+ printf("%s: Data Read Failed in PIO Mode\n",
+ __func__);
+ return;
+ }
+ for (i = 0; i < wml && size; i++) {
+ databuf = in_le32(®s->datport);
+ memcpy(buffer, &databuf, sizeof(databuf));
+ buffer += 4;
+ size -= 4;
+ }
}
blocks--;
}
} else {
+ wml = (wml & WML_WR_WML_MASK) >> 16;
blocks = data->blocks;
- buffer = (char *)data->src;
+ buffer = (char *)data->src; /* cast away 'const' */
while (blocks) {
timeout = PIO_TIMEOUT;
size = data->blocksize;
- irqstat = esdhc_read32(®s->irqstat);
- while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
- && --timeout);
- if (timeout <= 0) {
- printf("\nData Write Failed in PIO Mode.");
- return;
- }
- while (size && (!(irqstat & IRQSTAT_TC))) {
- udelay(100); /* Wait before last byte transfer complete */
- databuf = *((uint *)buffer);
- buffer += 4;
- size -= 4;
- irqstat = esdhc_read32(®s->irqstat);
- out_le32(®s->datport, databuf);
+ while (size &&
+ !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
+ int i;
+ u32 prsstat;
+
+ while (!((prsstat = esdhc_read32(®s->prsstat)) &
+ PRSSTAT_BWEN) && --timeout)
+ /* NOP */;
+ if (!(prsstat & PRSSTAT_BWEN)) {
+ printf("%s: Data Write Failed in PIO Mode\n",
+ __func__);
+ return;
+ }
+ for (i = 0; i < wml && size; i++) {
+ memcpy(&databuf, buffer, sizeof(databuf));
+ out_le32(®s->datport, databuf);
+ buffer += 4;
+ size -= 4;
+ }
}
blocks--;
}
{
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-
+ struct fsl_esdhc *regs = cfg->esdhc_base;
uint wml_value;
- wml_value = data->blocksize/4;
+ wml_value = data->blocksize / 4;
if (data->flags & MMC_DATA_READ) {
if (wml_value > WML_RD_WML_MAX)
if (wml_value > WML_WR_WML_MAX)
wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
- printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
- return TIMEOUT;
+ printf("The SD card is locked. Can not write to a locked card.\n");
+ return UNUSABLE_ERR;
}
+ flush_dcache_range((unsigned long)data->src,
+ (unsigned long)data->src + data->blocks * data->blocksize);
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
#endif
}
- esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
+ esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize);
/* Calculate the timeout period for data transactions */
/*
if (timeout > 14)
timeout = 14;
-
- if (timeout < 0)
+ else if (timeout < 0)
timeout = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
uint xfertyp;
uint irqstat;
struct fsl_esdhc_cfg *cfg = mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ volatile struct fsl_esdhc *regs = cfg->esdhc_base;
+ unsigned long start;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
return 0;
#endif
-
esdhc_write32(®s->irqstat, -1);
sync();
+ start = get_timer_masked();
/* Wait for the bus to be idle */
while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
- (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
- ;
+ (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) {
+ if (get_timer(start) > CONFIG_SYS_HZ) {
+ printf("%s: Timeout waiting for bus idle\n", __func__);
+ return TIMEOUT;
+ }
+ }
- while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
- ;
+ start = get_timer_masked();
+ while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) {
+ if (get_timer(start) > CONFIG_SYS_HZ)
+ return TIMEOUT;
+ }
/* Wait at least 8 SD clock cycles before the next command */
/*
/* Set up for a data transfer if we have one */
if (data) {
err = esdhc_setup_data(mmc, data);
- if(err)
+ if (err)
return err;
}
esdhc_write32(®s->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
esdhc_write32(®s->mixctrl,
- (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+ (esdhc_read32(®s->mixctrl) & ~0x7f) | (xfertyp & 0x7F)
+ | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
#else
esdhc_write32(®s->xfertyp, xfertyp);
#endif
+ /* Mask all irqs */
+ esdhc_write32(®s->irqsigen, 0);
+
+ start = get_timer_masked();
/* Wait for the command to complete */
- while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
- ;
+ while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) {
+ if (get_timer(start) > CONFIG_SYS_HZ) {
+ printf("%s: Timeout waiting for cmd completion\n", __func__);
+ return TIMEOUT;
+ }
+ }
+
+ if (data && (data->flags & MMC_DATA_READ))
+ check_and_invalidate_dcache_range(cmd, data);
irqstat = esdhc_read32(®s->irqstat);
goto out;
}
+ /* Switch voltage to 1.8V if CMD11 succeeded */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+ printf("Run CMD11 1.8V switch\n");
+ /* Sleep for 5 ms - max time for card to switch to 1.8V */
+ udelay(5000);
+ }
+
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
int timeout = 2500;
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
;
}
+
+ /* If this was CMD11, then notify that power cycle is needed */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
+ printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
}
- esdhc_write32(®s->irqstat, -1);
+ esdhc_write32(®s->irqstat, irqstat);
return err;
}
{
int div, pre_div;
struct fsl_esdhc_cfg *cfg = mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ volatile struct fsl_esdhc *regs = cfg->esdhc_base;
int sdhc_clk = cfg->sdhc_clk;
uint clk;
if ((sdhc_clk / (div * pre_div)) <= clock)
break;
- pre_div >>= 1;
+ pre_div >>= mmc->ddr_mode ? 2 : 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
static void esdhc_set_ios(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
/* Set the clock speed */
set_sysctl(mmc, mmc->clock);
static int esdhc_init(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
int timeout = 1000;
/* Reset the entire host controller */
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
+#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+#endif
+
return 0;
}
static int esdhc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
int timeout = 1000;
#ifdef CONFIG_ESDHC_DETECT_QUIRK
u32 caps, voltage_caps;
if (!cfg)
- return -1;
+ return -EINVAL;
regs = (struct fsl_esdhc *)cfg->esdhc_base;
#endif
if ((cfg->cfg.voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
- return -1;
+ return -EINVAL;
}
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+ cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+#endif
if (cfg->max_bus_width > 0) {
if (cfg->max_bus_width < 8)
{
struct fsl_esdhc_cfg *cfg;
- cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg = kzalloc(sizeof(struct fsl_esdhc_cfg), GFP_KERNEL);
+ if (!cfg)
+ return -ENOMEM;
+ cfg->esdhc_base = (void __iomem *)CONFIG_SYS_FSL_ESDHC_ADDR;
cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}