* Copyright (C) Linux Networx.
* Massive upgrade to work with the new intel gigabit NICs.
* <ebiederman at lnxi dot com>
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc.
*/
#include "e1000.h"
#define TOUT_LOOP 100000
-#undef virt_to_bus
-#define virt_to_bus(x) ((unsigned long)x)
+#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
#define mdelay(n) udelay((n)*1000)
-#define E1000_DEFAULT_PBA 0x000a0026
+#define E1000_DEFAULT_PCI_PBA 0x00000030
+#define E1000_DEFAULT_PCIE_PBA 0x000a0026
/* NIC specific static variables go here */
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
if (hw->mac_type == e1000_ich8lan)
return FALSE;
- if (hw->mac_type == e1000_82573) {
+ if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
eecd = E1000_READ_REG(hw, EECD);
/* Isolate bits 15 & 16 */
struct e1000_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd, i = 0;
- DEBUGOUT();
+ DEBUGFUNC();
if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
return -E1000_ERR_SWFW_SYNC;
eecd = E1000_READ_REG(hw, EECD);
- if (hw->mac_type != e1000_82573) {
+ if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
/* Request EEPROM Access */
if (hw->mac_type > e1000_82544) {
eecd |= E1000_EECD_REQ;
int32_t ret_val = E1000_SUCCESS;
uint16_t eeprom_size;
- DEBUGOUT();
+ DEBUGFUNC();
switch (hw->mac_type) {
case e1000_82542_rev2_0:
eeprom->use_eewr = FALSE;
break;
case e1000_82573:
+ case e1000_82574:
eeprom->type = e1000_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
case E1000_DEV_ID_82573L:
hw->mac_type = e1000_82573;
break;
+ case E1000_DEV_ID_82574L:
+ hw->mac_type = e1000_82574;
+ break;
case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
uint32_t ctrl_ext;
uint32_t icr;
uint32_t manc;
+ uint32_t pba = 0;
DEBUGFUNC();
+ /* get the correct pba value for both PCI and PCIe*/
+ if (hw->mac_type < e1000_82571)
+ pba = E1000_DEFAULT_PCI_PBA;
+ else
+ pba = E1000_DEFAULT_PCIE_PBA;
+
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
if (hw->mac_type == e1000_82542_rev2_0) {
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
}
- E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
+ E1000_WRITE_REG(hw, PBA, pba);
}
/******************************************************************************
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
break;
case e1000_82573:
+ case e1000_82574:
reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
reg_ctrl_ext &= ~(1 << 23);
reg_ctrl_ext |= (1 << 22);
| E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, TXDCTL1, ctrl);
break;
- }
-
- if (hw->mac_type == e1000_82573) {
- uint32_t gcr = E1000_READ_REG(hw, GCR);
- gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
- E1000_WRITE_REG(hw, GCR, gcr);
+ case e1000_82573:
+ case e1000_82574:
+ reg_data = E1000_READ_REG(hw, GCR);
+ reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
+ E1000_WRITE_REG(hw, GCR, reg_data);
}
#if 0
switch (hw->mac_type) {
case e1000_ich8lan:
case e1000_82573:
+ case e1000_82574:
hw->fc = e1000_fc_full;
break;
default:
int32_t ret_val;
uint16_t phy_data;
- DEBUGOUT();
+ DEBUGFUNC();
if (hw->phy_reset_disable)
return E1000_SUCCESS;
hw->phy_type = e1000_phy_gg82563;
break;
}
+ case BME1000_E_PHY_ID:
+ hw->phy_type = e1000_phy_bm;
+ break;
/* Fall Through */
default:
/* Should never have loaded on this device */
if (hw->phy_id == M88E1111_I_PHY_ID)
match = TRUE;
break;
+ case e1000_82574:
+ if (hw->phy_id == BME1000_E_PHY_ID)
+ match = TRUE;
+ break;
case e1000_80003es2lan:
if (hw->phy_id == GG82563_E_PHY_ID)
match = TRUE;
break;
case e1000_ich8lan:
case e1000_82573:
+ case e1000_82574:
/* The STATUS_TBIMODE bit is reserved or reused
* for the this device.
*/
static int
e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
{
+ void * nv_packet = (void *)packet;
struct e1000_hw *hw = nic->priv;
struct e1000_tx_desc *txp;
int i = 0;
txp = tx_base + tx_tail;
tx_tail = (tx_tail + 1) % 8;
- txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
+ txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
txp->upper.data = 0;
E1000_WRITE_REG(hw, TDT, tx_tail);
case e1000_82571:
case e1000_82572:
case e1000_82573:
+ case e1000_82574:
case e1000_80003es2lan:
hw->bus_type = e1000_bus_type_pci_express;
break;
int idx = 0;
u32 PciCommandWord;
+ DEBUGFUNC();
+
while (1) { /* Find PCI device(s) */
if ((devno = pci_find_devices(supported, idx++)) < 0) {
break;
}
nic = (struct eth_device *) malloc(sizeof (*nic));
+ if (!nic) {
+ printf("Error: e1000 - Can not alloc memory\n");
+ return 0;
+ }
+
hw = (struct e1000_hw *) malloc(sizeof (*hw));
+ if (!hw) {
+ free(nic);
+ printf("Error: e1000 - Can not alloc memory\n");
+ return 0;
+ }
+
+ memset(nic, 0, sizeof(*nic));
+ memset(hw, 0, sizeof(*hw));
+
hw->pdev = devno;
nic->priv = hw;
- nic->iobase = bus_to_phys(devno, iobase);
sprintf(nic->name, "e1000#%d", card_number);
hw->autoneg_failed = 0;
hw->autoneg = 1;
hw->get_link_status = TRUE;
- hw->hw_addr = (typeof(hw->hw_addr)) iobase;
+ hw->hw_addr =
+ pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
hw->mac_type = e1000_undefined;
/* MAC and Phy settings */
projects / karo-tx-uboot.git / blobdiff