static int inca_switch_init(struct eth_device *dev, bd_t * bis);
-static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
+static int inca_switch_send(struct eth_device *dev, void *packet, int length);
static int inca_switch_recv(struct eth_device *dev);
static void inca_switch_halt(struct eth_device *dev);
static void inca_init_switch_chip(void);
/* Initialize RxDMA.
*/
DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
-#if 0
- printf("RX status = 0x%08X\n", v);
-#endif
+ debug("RX status = 0x%08X\n", v);
/* Writing to the FRDA of CHANNEL.
*/
/* Initialize TxDMA.
*/
DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
-#if 0
- printf("TX status = 0x%08X\n", v);
-#endif
+ debug("TX status = 0x%08X\n", v);
/* Writing to the FRDA of CHANNEL.
*/
}
-static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
+static int inca_switch_send(struct eth_device *dev, void *packet, int length)
{
int i;
int res = -1;
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (6 << 16)); /* PHY_ANER */
+ (6 << 16)); /* MII_EXPANSION */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
} while (phyReg6 & (1 << 31));
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (4 << 16)); /* PHY_ANAR */
+ (4 << 16)); /* MII_ADVERTISE */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
} while (phyReg4 & (1 << 31));
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
- (5 << 16)); /* PHY_ANLPAR */
+ (5 << 16)); /* MII_LPA */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
} while (phyReg5 & (1 << 31));