Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[karo-tx-uboot.git] / drivers / net / mvgbe.h

diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index 7db5af450e292ba7ea5a6ae38d02a42ddacc027c..27a3f41e80cd7ffc6532d115074a3216a861ff71 100644 (file)
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -6,30 +6,12 @@
  * based on - Driver for MV64360X ethernet ports
  * Copyright (C) 2002 rabeeh@galileo.co.il
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __MVGBE_H__
 #define __MVGBE_H__
 
-#define MAX_MVGBE_DEVS 2       /*controller has two ports */
-
 /* PHY_BASE_ADR is board specific and can be configured */
 #if defined (CONFIG_PHY_BASE_ADR)
 #define PHY_BASE_ADR           CONFIG_PHY_BASE_ADR
@@ -86,6 +68,7 @@
        MVGBE_TX_BURST_SIZE_16_64BIT)
 
 /* Default port serial control value */
+#ifndef PORT_SERIAL_CONTROL_VALUE
 #define PORT_SERIAL_CONTROL_VALUE              ( \
        MVGBE_FORCE_LINK_PASS                   | \
        MVGBE_DIS_AUTO_NEG_FOR_DUPLX            | \
@@ -103,6 +86,7 @@
        MVGBE_CLR_EXT_LOOPBACK                  | \
        MVGBE_SET_FULL_DUPLEX_MODE              | \
        MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+#endif
 
 /* Tx WRR confoguration macros */
 #define PORT_MAX_TRAN_UNIT     0x24    /* MTU register (default) 9KByte */
@@ -308,10 +292,17 @@
 #define EBAR_TARGET_GUNIT                      0x00000007
 
 /* Window attrib */
+#if defined(CONFIG_DOVE)
+#define EBAR_DRAM_CS0                          0x00000000
+#define EBAR_DRAM_CS1                          0x00000000
+#define EBAR_DRAM_CS2                          0x00000000
+#define EBAR_DRAM_CS3                          0x00000000
+#else
 #define EBAR_DRAM_CS0                          0x00000E00
 #define EBAR_DRAM_CS1                          0x00000D00
 #define EBAR_DRAM_CS2                          0x00000B00
 #define EBAR_DRAM_CS3                          0x00000700
+#endif
 
 /* DRAM Target interface */
 #define EBAR_DRAM_NO_CACHE_COHERENCY           0x00000000