PCI: designware: Look for configuration space in 'reg', not 'ranges'

[karo-tx-linux.git] / drivers / pci / host / pcie-designware.c

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index c4e373294476a701278c93b4619610a9ed181f70..0b7b4558bcfdde263276d4473a46db5efd3c1709 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
 #include <linux/of_pci.h>
 #include <linux/pci.h>
 #include <linux/pci_regs.h>
+#include <linux/platform_device.h>
 #include <linux/types.h>
 
 #include "pcie-designware.h"
@@ -156,15 +157,17 @@ static struct irq_chip dw_msi_irq_chip = {
 };
 
 /* MSI int handler */
-void dw_handle_msi_irq(struct pcie_port *pp)
+irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
        unsigned long val;
        int i, pos, irq;
+       irqreturn_t ret = IRQ_NONE;
 
        for (i = 0; i < MAX_MSI_CTRLS; i++) {
                dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
                                (u32 *)&val);
                if (val) {
+                       ret = IRQ_HANDLED;
                        pos = 0;
                        while ((pos = find_next_bit(&val, 32, pos)) != 32) {
                                irq = irq_find_mapping(pp->irq_domain,
@@ -177,6 +180,8 @@ void dw_handle_msi_irq(struct pcie_port *pp)
                        }
                }
        }
+
+       return ret;
 }
 
 void dw_pcie_msi_init(struct pcie_port *pp)
@@ -392,11 +397,23 @@ static const struct irq_domain_ops msi_domain_ops = {
 int __init dw_pcie_host_init(struct pcie_port *pp)
 {
        struct device_node *np = pp->dev->of_node;
+       struct platform_device *pdev = to_platform_device(pp->dev);
        struct of_pci_range range;
        struct of_pci_range_parser parser;
+       struct resource *cfg_res;
        u32 val;
        int i;
 
+       cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
+       if (cfg_res) {
+               pp->config.cfg0_size = resource_size(cfg_res)/2;
+               pp->config.cfg1_size = resource_size(cfg_res)/2;
+               pp->cfg0_base = cfg_res->start;
+               pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
+       } else {
+               dev_err(pp->dev, "missing *config* reg space\n");
+       }
+
        if (of_pci_range_parser_init(&parser, np)) {
                dev_err(pp->dev, "missing ranges property\n");
                return -EINVAL;
@@ -429,6 +446,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
                        of_pci_range_to_resource(&range, np, &pp->cfg);
                        pp->config.cfg0_size = resource_size(&pp->cfg)/2;
                        pp->config.cfg1_size = resource_size(&pp->cfg)/2;
+                       pp->cfg0_base = pp->cfg.start;
+                       pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
                }
        }
 
@@ -441,8 +460,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
                }
        }
 
-       pp->cfg0_base = pp->cfg.start;
-       pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
        pp->mem_base = pp->mem.start;
 
        pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
@@ -639,7 +656,6 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                        int size, u32 *val)
 {
        struct pcie_port *pp = sys_to_pcie(bus->sysdata);
-       unsigned long flags;
        int ret;
 
        if (!pp) {
@@ -652,13 +668,11 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                return PCIBIOS_DEVICE_NOT_FOUND;
        }
 
-       spin_lock_irqsave(&pp->conf_lock, flags);
        if (bus->number != pp->root_bus_nr)
                ret = dw_pcie_rd_other_conf(pp, bus, devfn,
                                                where, size, val);
        else
                ret = dw_pcie_rd_own_conf(pp, where, size, val);
-       spin_unlock_irqrestore(&pp->conf_lock, flags);
 
        return ret;
 }
@@ -667,7 +681,6 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
                        int where, int size, u32 val)
 {
        struct pcie_port *pp = sys_to_pcie(bus->sysdata);
-       unsigned long flags;
        int ret;
 
        if (!pp) {
@@ -678,13 +691,11 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
        if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
                return PCIBIOS_DEVICE_NOT_FOUND;
 
-       spin_lock_irqsave(&pp->conf_lock, flags);
        if (bus->number != pp->root_bus_nr)
                ret = dw_pcie_wr_other_conf(pp, bus, devfn,
                                                where, size, val);
        else
                ret = dw_pcie_wr_own_conf(pp, where, size, val);
-       spin_unlock_irqrestore(&pp->conf_lock, flags);
 
        return ret;
 }