85xx: add ability to upload QE firmware

[karo-tx-uboot.git] / drivers / qe / qe.h

diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 400b1a6f603839444483f7f13c0022939277da08..4c96c67ff34521e5fc19bf1944062f52c1951392 100644 (file)
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -222,6 +222,60 @@ typedef enum qe_clock {
 
 #define QE_SDEBCR_BA_MASK              0x01FFFFFF
 
+/* Communication Processor */
+#define QE_CP_CERCR_MEE                0x8000  /* Multi-user RAM ECC enable */
+#define QE_CP_CERCR_IEE                0x4000  /* Instruction RAM ECC enable */
+#define QE_CP_CERCR_CIR                0x0800  /* Common instruction RAM */
+
+/* I-RAM */
+#define QE_IRAM_IADD_AIE       0x80000000      /* Auto Increment Enable */
+#define QE_IRAM_IADD_BADDR     0x00080000      /* Base Address */
+
+/* Structure that defines QE firmware binary files.
+ *
+ * See doc/README.qe_firmware for a description of these fields.
+ */
+struct qe_firmware {
+       struct qe_header {
+               u32 length;  /* Length of the entire structure, in bytes */
+               u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
+               u8 version;     /* Version of this layout. First ver is '1' */
+       } header;
+       u8 id[62];      /* Null-terminated identifier string */
+       u8 split;       /* 0 = shared I-RAM, 1 = split I-RAM */
+       u8 count;       /* Number of microcode[] structures */
+       struct {
+               u16 model;      /* The SOC model  */
+               u8 major;               /* The SOC revision major */
+               u8 minor;               /* The SOC revision minor */
+       } __attribute__ ((packed)) soc;
+       u8 padding[4];                  /* Reserved, for alignment */
+       u64 extended_modes;             /* Extended modes */
+       u32 vtraps[8];          /* Virtual trap addresses */
+       u8 reserved[4];                 /* Reserved, for future expansion */
+       struct qe_microcode {
+               u8 id[32];              /* Null-terminated identifier */
+               u32 traps[16];       /* Trap addresses, 0 == ignore */
+               u32 eccr;       /* The value for the ECCR register */
+               u32 iram_offset;     /* Offset into I-RAM for the code */
+               u32 count;      /* Number of 32-bit words of the code */
+               u32 code_offset;     /* Offset of the actual microcode */
+               u8 major;               /* The microcode version major */
+               u8 minor;               /* The microcode version minor */
+               u8 revision;            /* The microcode version revision */
+               u8 padding;             /* Reserved, for alignment */
+               u8 reserved[4];         /* Reserved, for future expansion */
+       } __attribute__ ((packed)) microcode[1];
+       /* All microcode binaries should be located here */
+       /* CRC32 should be located here, after the microcode binaries */
+} __attribute__ ((packed));
+
+struct qe_firmware_info {
+       char id[64];            /* Firmware name */
+       u32 vtraps[8];          /* Virtual trap addresses */
+       u64 extended_modes;     /* Extended modes */
+};
+
 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
 uint qe_muram_alloc(uint size, uint align);
@@ -233,5 +287,7 @@ void qe_reset(void);
 void qe_assign_page(uint snum, uint para_ram_base);
 int qe_set_brg(uint brg, uint rate);
 int qe_set_mii_clk_src(int ucc_num);
+int qe_upload_firmware(const struct qe_firmware *firmware);
+struct qe_firmware_info *qe_get_firmware_info(void);
 
 #endif /* __QE_H__ */