net: tsec: Fix and cleanup tsec_mcast_addr()

[karo-tx-uboot.git] / drivers / video / ipu_regs.h

diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 93b195f2ce15c3949a0f99644014fc02a710cf55..73e57ea999a4952ce2f3d27e3720b8cf3556c150 100644 (file)
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -8,23 +8,7 @@
  *
  * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __IPU_REGS_INCLUDED__
@@ -47,14 +31,24 @@
 #define IPU_SMFC_REG_BASE      0x00050000
 #define IPU_DC_REG_BASE                0x00058000
 #define IPU_DMFC_REG_BASE      0x00060000
+#define IPU_VDI_REG_BASE       0x00680000
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #define IPU_CPMEM_REG_BASE     0x01000000
 #define IPU_LUT_REG_BASE       0x01020000
 #define IPU_SRM_REG_BASE       0x01040000
 #define IPU_TPM_REG_BASE       0x01060000
 #define IPU_DC_TMPL_REG_BASE   0x01080000
 #define IPU_ISP_TBPR_REG_BASE  0x010C0000
-#define IPU_VDI_REG_BASE       0x00680000
+#elif defined(CONFIG_MX6)
+#define IPU_CPMEM_REG_BASE     0x00100000
+#define IPU_LUT_REG_BASE       0x00120000
+#define IPU_SRM_REG_BASE       0x00140000
+#define IPU_TPM_REG_BASE       0x00160000
+#define IPU_DC_TMPL_REG_BASE   0x00180000
+#define IPU_ISP_TBPR_REG_BASE  0x001C0000
+#endif
 
+#define IPU_CTRL_BASE_ADDR     (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
 
 extern u32 *ipu_dc_tmpl_reg;