dev_vdbg(), available with -DVERBOSE_DEBUG

[karo-tx-linux.git] / include / asm-parisc / system.h

diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h
index 863876134b2ca9cce106096cfff6551689403c79..21fbfc5afd027a2ca6dc5e6ea7ad4415cfe03d1f 100644 (file)
--- a/include/asm-parisc/system.h
+++ b/include/asm-parisc/system.h
@@ -34,7 +34,7 @@ struct pa_psw {
        unsigned int i:1;
 };
 
-#ifdef __LP64__
+#ifdef CONFIG_64BIT
 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
 #else
 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
@@ -143,8 +143,6 @@ static inline void set_eiem(unsigned long val)
 #define read_barrier_depends()         do { } while(0)
 
 #define set_mb(var, value)             do { var = value; mb(); } while (0)
-#define set_wmb(var, value)            do { var = value; wmb(); } while (0)
-
 
 #ifndef CONFIG_PA20
 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
@@ -155,13 +153,14 @@ static inline void set_eiem(unsigned long val)
    type and dynamically select the 16-byte aligned int from the array
    for the semaphore.  */
 
-#define __PA_LDCW_ALIGNMENT 16
-#define __ldcw_align(a) ({ \
-  unsigned long __ret = (unsigned long) &(a)->lock[0];                 \
-  __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); \
-  (volatile unsigned int *) __ret;                                      \
+#define __PA_LDCW_ALIGNMENT    16
+#define __ldcw_align(a) ({                                     \
+       unsigned long __ret = (unsigned long) &(a)->lock[0];    \
+       __ret = (__ret + __PA_LDCW_ALIGNMENT - 1)               \
+               & ~(__PA_LDCW_ALIGNMENT - 1);                   \
+       (volatile unsigned int *) __ret;                        \
 })
-#define LDCW   "ldcw"
+#define __LDCW "ldcw"
 
 #else /*CONFIG_PA20*/
 /* From: "Jim Hull" <jim.hull of hp.com>
@@ -171,24 +170,24 @@ static inline void set_eiem(unsigned long val)
    they only require "natural" alignment (4-byte for ldcw, 8-byte for
    ldcd). */
 
-#define __PA_LDCW_ALIGNMENT 4
+#define __PA_LDCW_ALIGNMENT    4
 #define __ldcw_align(a) ((volatile unsigned int *)a)
-#define LDCW   "ldcw,co"
+#define __LDCW "ldcw,co"
 
 #endif /*!CONFIG_PA20*/
 
 /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
-#define __ldcw(a) ({ \
-       unsigned __ret; \
-       __asm__ __volatile__(LDCW " 0(%1),%0" : "=r" (__ret) : "r" (a)); \
-       __ret; \
+#define __ldcw(a) ({                                           \
+       unsigned __ret;                                         \
+       __asm__ __volatile__(__LDCW " 0(%1),%0"                 \
+               : "=r" (__ret) : "r" (a));                      \
+       __ret;                                                  \
 })
 
 #ifdef CONFIG_SMP
 # define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
 #endif
 
-#define KERNEL_START (0x10100000 - 0x1000)
 #define arch_align_stack(x) (x)
 
 #endif