mpc85xx: Add support for the P2020

[karo-tx-uboot.git] / include / asm-ppc / immap_85xx.h

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e5046bef3217624336838ad10f6a1f8747df11cd..ed8ddeda1cc90db85b436381ba96abd3931b0363 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -58,7 +58,23 @@ typedef struct ccsr_local_ecm {
        uint    lawbar7;        /* 0xce8 - Local Access Window 7 Base Address Register */
        char    res19[4];
        uint    lawar7;         /* 0xcf0 - Local Access Window 7 Attributes Register */
-       char    res20[780];     /* XXX: LAW 8, LAW9 for 8572 */
+       char    res19_8a[20];
+       uint    lawbar8;        /* 0xd08 - Local Access Window 8 Base Address Register */
+       char    res19_8b[4];
+       uint    lawar8;         /* 0xd10 - Local Access Window 8 Attributes Register */
+       char    res19_9a[20];
+       uint    lawbar9;        /* 0xd28 - Local Access Window 9 Base Address Register */
+       char    res19_9b[4];
+       uint    lawar9;         /* 0xd30 - Local Access Window 9 Attributes Register */
+       char    res19_10a[20];
+       uint    lawbar10;       /* 0xd48 - Local Access Window 10 Base Address Register */
+       char    res19_10b[4];
+       uint    lawar10;        /* 0xd50 - Local Access Window 10 Attributes Register */
+       char    res19_11a[20];
+       uint    lawbar11;       /* 0xd68 - Local Access Window 11 Base Address Register */
+       char    res19_11b[4];
+       uint    lawar11;        /* 0xd70 - Local Access Window 11 Attributes Register */
+       char    res20[652];
        uint    eebacr;         /* 0x1000 - ECM CCB Address Configuration Register */
        char    res21[12];
        uint    eebpcr;         /* 0x1010 - ECM CCB Port Configuration Register */
@@ -119,7 +135,12 @@ typedef struct ccsr_ddr {
        uint    ddr_sr_cntr;            /* 0x217C - DDR self refresh counter */
        uint    ddr_sdram_rcw_1;        /* 0x2180 - DDR Register Control Words 1 */
        uint    ddr_sdram_rcw_2;        /* 0x2184 - DDR Register Control Words 2 */
-       char    res8_1b[2672];
+       char    res8_1b[2456];
+       uint    ddr_dsr1;               /* 0x2B20 - DDR Debug Status Register 1 */
+       uint    ddr_dsr2;               /* 0x2B24 - DDR Debug Status Register 2 */
+       uint    ddr_cdr1;               /* 0x2B28 - DDR Control Driver Register 1 */
+       uint    ddr_cdr2;               /* 0x2B2C - DDR Control Driver Register 2 */
+       char    res8_1c[200];
        uint    ip_rev1;                /* 0x2BF8 - DDR IP Block Revision 1 */
        uint    ip_rev2;                /* 0x2BFC - DDR IP Block Revision 2 */
        char    res8_2[512];