powerpc: merge uaccess.h

[karo-tx-linux.git] / include / asm-ppc / pgtable.h

diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index c41c7958ea1fcbc77c809743e853902f5d29c40a..b28a713ba862e48754afc3d409060d50153ad1a2 100644 (file)
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -227,21 +227,21 @@ extern unsigned long ioremap_bot, ioremap_base;
  *     doesn't support SMP. So we can use this as software bit, like
  *     DIRTY.
  *
- * PPC Book-E Linux implementation uses PPC HW PTE bit field definition,
- * even it doesn't have HW PTE. 0-11th LSB of PTE stand for memory
- * protection-related function. (See PTE structure in include/asm-ppc/mmu.h)
- * Definition of _PAGE_XXX in "include/asm-ppc/pagetable.h" stands for
- * above bits. Note that those bits values are CPU dependent, not
- * architecture.
+ * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
+ * for memory protection related functions (see PTE structure in
+ * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
+ * above bits.  Note that the bit values are CPU specific, not architecture
+ * specific.
  *
- * Kernel PTE entry holds arch-dependent swp_entry structure under certain
- * situation. In other words, in such situation, some portion of PTE bits
- * are used as swp_entry. In PPC implementation, 3-24th LSB are shared with
- * swp_entry, however 0-2nd three LSB still hold protection values.
- * That means three protection bits are reserved for both PTE and SWAP
- * entry at the most three LSBs.
+ * The kernel PTE entry holds an arch-dependent swp_entry structure under
+ * certain situations. In other words, in such situations some portion of
+ * the PTE bits are used as a swp_entry. In the PPC implementation, the
+ * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
+ * hold protection values. That means the three protection bits are
+ * reserved for both PTE and SWAP entry at the most significant three
+ * LSBs.
  *
- * There are three protection bits available for SWAP entry;
+ * There are three protection bits available for SWAP entry:
  *     _PAGE_PRESENT
  *     _PAGE_FILE
  *     _PAGE_HASHPTE (if HW has)
@@ -705,7 +705,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 
 struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
                                     unsigned long size, pgprot_t vma_prot);
 #define __HAVE_PHYS_MEM_ACCESS_PROT
 
@@ -812,15 +812,6 @@ extern void kernel_set_cachemode (unsigned long address, unsigned long size,
 #ifdef CONFIG_PHYS_64BIT
 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
                        unsigned long paddr, unsigned long size, pgprot_t prot);
-static inline int io_remap_page_range(struct vm_area_struct *vma,
-                                       unsigned long vaddr,
-                                       unsigned long paddr,
-                                       unsigned long size,
-                                       pgprot_t prot)
-{
-       phys_addr_t paddr64 = fixup_bigphys_addr(paddr, size);
-       return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
-}
 
 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                                        unsigned long vaddr,
@@ -832,8 +823,6 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
        return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
 }
 #else
-#define io_remap_page_range(vma, vaddr, paddr, size, prot)             \
-               remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)                \
                remap_pfn_range(vma, vaddr, pfn, size, prot)
 #endif