/* watchdog disabled */
#undef CONFIG_WATCHDOG
/* SPD EEPROM (sdram speed config) disabled */
-#undef CONFIG_SPD_EEPRO
+#undef CONFIG_SPD_EEPROM
#undef SPD_EEPROM_ADDRESS
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
+#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */