Coding Style cleanup: replace leading SPACEs by TABs

[karo-tx-uboot.git] / include / configs / MPC8315ERDB.h

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 0ae1d998eac95b63c44777f9e14b2e35c297f2cc..fef19d4b5fe840a403b607b5b9b54336be1ddb7c 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -3,23 +3,7 @@
  *
  * Dave Liu <daveliu@freescale.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -229,20 +213,21 @@
 
                                        /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000016 /* 8MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_8MB)
 
 #define CONFIG_SYS_NOR_BR_PRELIM       (CONFIG_SYS_FLASH_BASE \
-                               | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM       ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
-                               | OR_GPCM_EAD)
+                                       | BR_PS_16      /* 16 bit port */ \
+                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
+                                       | BR_V)         /* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM       (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+                                       | OR_UPM_XAM \
+                                       | OR_GPCM_CSNT \
+                                       | OR_GPCM_ACS_DIV2 \
+                                       | OR_GPCM_XACS \
+                                       | OR_GPCM_SCY_15 \
+                                       | OR_GPCM_TRLX_SET \
+                                       | OR_GPCM_EHTR_SET \
+                                       | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 /* 127 64KB sectors and 8 8KB top sectors per device */
@@ -273,7 +258,8 @@
 #define CONFIG_MTD_NAND_VERIFY_WRITE   1
 #define CONFIG_CMD_NAND                        1
 #define CONFIG_NAND_FSL_ELBC           1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_BLOCK_SIZE     16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 
 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
@@ -282,11 +268,12 @@
 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 
 #define CONFIG_SYS_NAND_BR_PRELIM      (CONFIG_SYS_NAND_BASE \
-                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
                                | BR_PS_8               /* 8 bit port */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM      (0xFFFF8000     /* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM      \
+                               (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
                                | OR_FCM_CSCT \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
@@ -308,7 +295,7 @@
 #endif
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E      /* 32KB  */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
 
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
@@ -337,9 +324,6 @@
 
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
 
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
@@ -347,13 +331,12 @@
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
 /* I2C */
-#define CONFIG_HARD_I2C                /* I2C with hardware support */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED           400000 /* I2C speed and slave addr */
-#define CONFIG_SYS_I2C_SLAVE           0x7F
-#define CONFIG_SYS_I2C_NOPROBES                {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET          0x3000
-#define CONFIG_SYS_I2C2_OFFSET         0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       400000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
+#define CONFIG_SYS_I2C_NOPROBES                { {0, 0x51} }
 
 /*
  * Board info - revision and where boot from
@@ -405,6 +388,7 @@
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000
 
 #define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE
 
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */