#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
+#define PIXIS_VSPEED2_TSEC1SER 0x2
+#define PIXIS_VSPEED2_TSEC3SER 0x1
+#define PIXIS_VCFGEN1_TSEC1SER 0x20
+#define PIXIS_VCFGEN1_TSEC3SER 0x40
/* define to use L1 as initial stack */