ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updates

[karo-tx-uboot.git] / include / configs / PLU405.h

diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 4acbcd5e1ca7d2e59028ce7e98e50c807675c78a..0bd77c07b653711a4ddcb57f773644d56a27cdc2 100644 (file)
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -177,7 +177,8 @@
 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CFG_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -287,6 +288,7 @@
 #define CFG_I2C_SLAVE          0x7F
 
 #define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT24WC08             */
+#define CFG_EEPROM_WREN         1
 
 /* CAT24WC08/16... */
 #define CFG_I2C_EEPROM_ADDR_LEN 1      /* Bytes of address             */
@@ -298,16 +300,6 @@
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs, older 405 ppc's   */
-                                       /* have only 8kB, 16kB is save here     */
-#define CFG_CACHELINE_SIZE     32      /* ...                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
-#endif
-
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
@@ -388,15 +380,16 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH         0x40000550
+#define CFG_GPIO0_OSRH         0x00000550
 #define CFG_GPIO0_OSRL         0x00000110
 #define CFG_GPIO0_ISR1H                0x00000000
 #define CFG_GPIO0_ISR1L                0x15555445
 #define CFG_GPIO0_TSRH         0x00000000
 #define CFG_GPIO0_TSRL         0x00000000
-#define CFG_GPIO0_TCR          0xF7FE0014
+#define CFG_GPIO0_TCR          0x77FE0014
 
 #define CFG_DUART_RST          (0x80000000 >> 14)
+#define CFG_EEPROM_WP          (0x80000000 >> 0)
 
 /*
  * Internal Definitions