driver/i2c/mxc: Enable I2C bus 3 and 4

[karo-tx-uboot.git] / include / configs / ls1021atwr.h

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a3271fed0599434ef7bd191386bb32b24868d441..045a4094eb602aa7dd0c490b5c7c7776356ba7aa 100644 (file)
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -9,7 +9,6 @@
 
 #include <config_cmd_default.h>
 
-#define CONFIG_LS102XA
 
 #define CONFIG_SYS_GENERIC_BOARD
 
@@ -186,11 +185,16 @@
 /*
  * Serial Port
  */
+#ifdef CONFIG_LPUART
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
 #define CONFIG_CONS_INDEX              1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+#endif
 
 #define CONFIG_BAUDRATE                        115200
 
@@ -200,6 +204,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* EEPROM */
 #ifndef CONFIG_SD_BOOT
@@ -298,6 +303,30 @@
 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE      0x00001000      /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF  0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE      0x00001000      /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS         0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF    0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE                0x00010000      /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS                0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF   0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE       0x08000000      /* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
@@ -312,15 +341,30 @@
 #define CONFIG_CMD_IMLS
 #endif
 
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ          12500000
+#define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR
+
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
 
 #define CONFIG_BOOTDELAY               3
 
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+       "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+       "initrd_high=0xcfffffff\0"      \
+       "fdt_high=0xcfffffff\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
        "initrd_high=0xcfffffff\0"      \
        "fdt_high=0xcfffffff\0"
+#endif
 
 /*
  * Miscellaneous configurable options
@@ -344,6 +388,8 @@
 
 #define CONFIG_SYS_LOAD_ADDR           0x82000000
 
+#define CONFIG_LS102XA_STREAM_ID
+
 /*
  * Stack sizes
  * The stack sizes are set up in start.S using the settings below