ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)

[karo-tx-uboot.git] / include / configs / lwmon5.h

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index c4b7c4ee504196abacaad0b4e284f909ca3cd5b4..14a200d3e44ac960e6b810d09d82a21028d20c7f 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -34,6 +34,7 @@
 #define CONFIG_SYS_CLK_FREQ    33300000        /* external freq to pll */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* Call board_early_init_f      */
+#define CONFIG_BOARD_POSTCLK_INIT 1    /* Call board_postclk_init      */
 #define CONFIG_MISC_INIT_R     1       /* Call misc_init_r             */
 #define CONFIG_ADD_RAM_INFO    1       /* Print additional info        */
 
@@ -46,7 +47,7 @@
 
 #define CFG_BOOT_BASE_ADDR     0xf0000000
 #define CFG_SDRAM_BASE         0x00000000      /* _must_ be 0          */
-#define CFG_FLASH_BASE         0xfc000000      /* start of FLASH       */
+#define CFG_FLASH_BASE         0xf8000000      /* start of FLASH       */
 #define CFG_MONITOR_BASE       TEXT_BASE
 #define CFG_LIME_BASE_0         0xc0000000
 #define CFG_LIME_BASE_1         0xc1000000
@@ -74,11 +75,13 @@
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache    */
 #define CFG_INIT_RAM_OCM       1               /* OCM as init ram      */
 #define CFG_INIT_RAM_ADDR      CFG_OCM_BASE    /* OCM                  */
+#define CFG_OCM_DATA_ADDR      CFG_OCM_BASE
 
 #define CFG_INIT_RAM_END       (4 << 10)
 #define CFG_GBL_DATA_SIZE      256             /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+#define CFG_POST_WORD_ADDR     (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET     CFG_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -103,9 +106,11 @@
 #define CFG_FLASH_CFI                          /* The flash is CFI compatible  */
 #define CFG_FLASH_CFI_DRIVER                   /* Use common CFI driver        */
 
-#define CFG_FLASH_BANKS_LIST   { CFG_FLASH_BASE }
+#define CFG_FLASH0             0xFC000000
+#define CFG_FLASH1             0xF8000000
+#define CFG_FLASH_BANKS_LIST   { CFG_FLASH1, CFG_FLASH0 }
 
-#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
 #define CFG_MAX_FLASH_SECT     512     /* max number of sectors on one chip    */
 
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
@@ -133,6 +138,9 @@
 #define CONFIG_DDR_DATA_EYE    1               /* use DDR2 optimization        */
 #if 0 /* test-only: disable ECC for now */
 #define CONFIG_DDR_ECC         1               /* enable ECC                   */
+
+/* POST support */
+#define CONFIG_POST            (CFG_POST_ECC)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -152,10 +160,16 @@
 
 #define CONFIG_RTC_PCF8563     1               /* enable Philips PCF8563 RTC   */
 #define CFG_I2C_RTC_ADDR       0x51            /* Philips PCF8563 RTC address  */
+#define CFG_I2C_KEYBD_ADDR     0x56            /* PIC LWE keyboard             */
+
+#define        CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
+#if 0
+#define        CONFIG_AUTOBOOT_KEYED           /* Enable "password" protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR      "  "    /* "password"   */
+#endif
 
-#define CONFIG_PREBOOT "echo;"                                         \
-       "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-       "echo"
+#define        CONFIG_PREBOOT          "setenv bootdelay 15"
 
 #undef CONFIG_BOOTARGS
 
@@ -203,6 +217,7 @@
 #define CONFIG_PHY_ADDR                3       /* PHY address, See schematics  */
 
 #define CONFIG_PHY_RESET        1      /* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY 300
 
 #define CONFIG_HAS_ETH0
 #define CFG_RX_ETH_BUFFER      32      /* Number of ethernet rx buffers & descriptors */
@@ -313,7 +328,7 @@
 
 /* Memory Bank 0 (NOR-FLASH) initialization                                    */
 #define CFG_EBC_PB0AP          0x03050200
-#define CFG_EBC_PB0CR          (CFG_FLASH | 0xdc000)
+#define CFG_EBC_PB0CR          (CFG_FLASH | 0xfc000)
 
 /* Memory Bank 1 (Lime) initialization                                         */
 #define CFG_EBC_PB1AP          0x01004380
@@ -333,14 +348,24 @@
  * Graphics (Fujitsu Lime)
  *----------------------------------------------------------------------*/
 /* SDRAM Clock frequency adjustment register */
-#define CFG_LIME_SDRAM_CLOCK   0xC1FC0000
-/* Lime Clock frequency is to set 133MHz */
+#define CFG_LIME_SDRAM_CLOCK   0xC1FC0038
+/* Lime Clock frequency is to set 100MHz */
+#define CFG_LIME_CLOCK_100MHZ  0x00000
+#if 0
+/* Lime Clock frequency for 133MHz */
 #define CFG_LIME_CLOCK_133MHZ  0x10000
+#endif
 
 /* SDRAM Parameter register */
 #define CFG_LIME_MMR           0xC1FCFFFC
-/* SDRAM parameter value */
+/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+   and pixel flare on display when 133MHz was configured. According to
+   SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+#ifdef CFG_LIME_CLOCK_133MHZ
+#define CFG_LIME_MMR_VALUE     0x414FB7F3
+#else
 #define CFG_LIME_MMR_VALUE     0x414FB7F2
+#endif
 
 /*-----------------------------------------------------------------------
  * GPIO Setup