#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif
+/*
+ * APBH DMA
+ */
+#define CONFIG_APBH_DMA
+
/*
* NAND
*/
#define CONFIG_ENV_SIZE (16 * 1024)
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
-#define CONFIG_APBH_DMA
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_CS 2
+#define CONFIG_SF_DEFAULT_CS 2
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000