ppc4xx/Canyonlands added USB board callbacks

[karo-tx-uboot.git] / include / configs / pm9261.h

diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 47bb8c09aa415499c3b14512013076006f86ad7f..a0b00e9706a5beda3586ae17a29b6554887767e1 100644 (file)
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -28,8 +28,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_CPU_NAME       "AT91SAM9261"
 
@@ -51,26 +49,26 @@
 /* clocks */
 /* CKGR_MOR - enable main osc. */
 #define CONFIG_SYS_MOR_VAL                                             \
-               (AT91_PMC_MOSCEN |                                      \
+               (AT91_PMC_MOR_MOSCEN |                                  \
                 (255 << 8))            /* Main Oscillator Start-up Time */
 #define CONFIG_SYS_PLLAR_VAL                                           \
-               (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
-                AT91_PMC_OUT |                                         \
+               (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+                AT91_PMC_PLLXR_OUT(3) |                                                \
                 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define        CONFIG_SYS_MCKR1_VAL            \
-               (AT91_PMC_CSS_SLOW |    \
-                AT91_PMC_PRES_1 |      \
-                AT91SAM9_PMC_MDIV_2 |  \
-                AT91_PMC_PDIV_1)
+               (AT91_PMC_MCKR_CSS_SLOW |       \
+                AT91_PMC_MCKR_PRES_1 | \
+                AT91_PMC_MCKR_MDIV_2 | \
+                AT91_PMC_MCKR_PLLADIV_1)
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define        CONFIG_SYS_MCKR2_VAL            \
-               (AT91_PMC_CSS_PLLA |    \
-                AT91_PMC_PRES_1 |      \
-                AT91SAM9_PMC_MDIV_2 |  \
-                AT91_PMC_PDIV_1)
+               (AT91_PMC_MCKR_CSS_PLLA |       \
+                AT91_PMC_MCKR_PRES_1 | \
+                AT91_PMC_MCKR_MDIV_2 | \
+                AT91_PMC_MCKR_PLLADIV_1)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOC_PDR_VAL1       0xFFFF0000
@@ -79,7 +77,7 @@
 
 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
 #define CONFIG_SYS_MATRIX_EBICSA_VAL           \
-       (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
+       (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
@@ -122,32 +120,32 @@
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 #define CONFIG_SYS_SMC0_SETUP0_VAL                                     \
-               (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |   \
-                AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+               (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
+                AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 #define CONFIG_SYS_SMC0_PULSE0_VAL                                     \
-               (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |   \
-                AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+               (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
+                AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 #define CONFIG_SYS_SMC0_CYCLE0_VAL     \
-               (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+               (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 #define CONFIG_SYS_SMC0_MODE0_VAL                              \
-               (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |       \
-                AT91_SMC_DBW_16 |                              \
-                AT91_SMC_TDFMODE |                             \
-                AT91_SMC_TDF_(6))
+               (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
+                AT91_SMC_MODE_DBW_16 |                         \
+                AT91_SMC_MODE_TDF |                            \
+                AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
 #define CONFIG_SYS_RSTC_RMR_VAL                        \
                (AT91_RSTC_KEY |                \
-               AT91_RSTC_PROCRST |             \
-               AT91_RSTC_RSTTYP_WAKEUP |       \
-               AT91_RSTC_RSTTYP_WATCHDOG)
+               AT91_RSTC_CR_PROCRST |          \
+               AT91_RSTC_MR_ERSTL(1) | \
+               AT91_RSTC_MR_ERSTL(2))
 
 /* Disable Watchdog */
 #define CONFIG_SYS_WDTC_WDMR_VAL                               \
-               (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |       \
-                AT91_WDT_WDV |                                 \
-                AT91_WDT_WDDIS |                               \
-                AT91_WDT_WDD)
+               (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+                AT91_WDT_MR_WDV(0xfff) |                                       \
+                AT91_WDT_MR_WDDIS |                            \
+                AT91_WDT_MR_WDD(0xfff))
 
 #define CONFIG_CMDLINE_TAG     1       /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS 1
@@ -180,9 +178,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define        CONFIG_RED_LED          AT91_PIN_PC12
-#define        CONFIG_GREEN_LED        AT91_PIN_PC13
-#define        CONFIG_YELLOW_LED       AT91_PIN_PC15
+#define        CONFIG_RED_LED          AT91_PIO_PORTC, 12
+#define        CONFIG_GREEN_LED        AT91_PIO_PORTC, 13
+#define        CONFIG_YELLOW_LED       AT91_PIO_PORTC, 15
 
 #define CONFIG_BOOTDELAY       3
 
@@ -200,7 +198,6 @@
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_IMLS
@@ -236,8 +233,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 22)
 /* our CLE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE               (1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN              AT91_PIN_PA16
+#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN              AT91_PIO_PORTA, 16
 
 /* NOR flash */
 #define CONFIG_SYS_FLASH_CFI                   1