fpga: add #define for Altera Cyclone EP3C5

[karo-tx-uboot.git] / include / fsl_esdhc.h

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 01b7dec18875696bd3911a8ff54836bb6a2b3800..8418bf7f47aa177af9bcd029276646c5525e15b9 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -2,7 +2,7 @@
  * FSL SD/MMC Defines
  *-------------------------------------------------------------------
  *
- * Copyright 2007-2008, Freescale Semiconductor, Inc
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -39,6 +39,7 @@
 #define SYSCTL_PEREN           0x00000004
 #define SYSCTL_HCKEN           0x00000002
 #define SYSCTL_IPGEN           0x00000001
+#define SYSCTL_RSTA            0x01000000
 
 #define IRQSTAT                        0x0002e030
 #define IRQSTAT_DMAE           (0x10000000)
@@ -89,6 +90,7 @@
 #define PRSSTAT_CDPL           (0x00040000)
 #define PRSSTAT_CINS           (0x00010000)
 #define PRSSTAT_BREN           (0x00000800)
+#define PRSSTAT_BWEN           (0x00000400)
 #define PRSSTAT_DLA            (0x00000004)
 #define PRSSTAT_CICHB          (0x00000002)
 #define PRSSTAT_CIDHB          (0x00000001)
@@ -120,6 +122,7 @@
 #define XFERTYP_DMAEN          0x00000001
 
 #define CINS_TIMEOUT           1000
+#define PIO_TIMEOUT            100000
 
 #define DSADDR         0x2e004
 
@@ -132,6 +135,21 @@
 
 #define WML            0x2e044
 #define WML_WRITE      0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX         0x80
+#define WML_WR_WML_MAX         0x80
+#define WML_RD_WML_MAX_VAL     0x0
+#define WML_WR_WML_MAX_VAL     0x0
+#define WML_RD_WML_MASK                0x7f
+#define WML_WR_WML_MASK                0x7f0000
+#else
+#define WML_RD_WML_MAX         0x10
+#define WML_WR_WML_MAX         0x80
+#define WML_RD_WML_MAX_VAL     0x10
+#define WML_WR_WML_MAX_VAL     0x80
+#define WML_RD_WML_MASK        0xff
+#define WML_WR_WML_MASK        0xff0000
+#endif
 
 #define BLKATTR                0x2e004
 #define BLKATTR_CNT(x) ((x & 0xffff) << 16)
@@ -148,7 +166,6 @@
 struct fsl_esdhc_cfg {
        u32     esdhc_base;
        u32     no_snoop;
-       u32     clk_enable;
 };
 
 /* Select the correct accessors depending on endianess */