85xx: Fix the incorrect register used for DDR erratum1

[karo-tx-uboot.git] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 70a4de70dfa2376ba2b598f3c07ff96d4fe89aab..ccf1077dccc926bea1233e37a3acd13f7dc5c112 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -350,7 +350,9 @@
 /* ATR - Arbiter Timers Register
  */
 #define ATR_DTO                                0x00FF0000      /* Data time out */
+#define ATR_DTO_SHIFT                  16
 #define ATR_ATO                                0x000000FF      /* Address time out */
+#define ATR_ATO_SHIFT                  0
 
 /* AER - Arbiter Event Register
  */
@@ -364,10 +366,15 @@
 /* AEATR - Arbiter Event Address Register
  */
 #define AEATR_EVENT                    0x07000000      /* Event type */
+#define AEATR_EVENT_SHIFT              24
 #define AEATR_MSTR_ID                  0x001F0000      /* Master Id */
+#define AEATR_MSTR_ID_SHIFT            16
 #define AEATR_TBST                     0x00000800      /* Transfer burst */
+#define AEATR_TBST_SHIFT               11
 #define AEATR_TSIZE                    0x00000700      /* Transfer Size */
+#define AEATR_TSIZE_SHIFT              8
 #define AEATR_TTYPE                    0x0000001F      /* Transfer Type */
+#define AEATR_TTYPE_SHIFT              0
 
 /* HRCWL - Hard Reset Configuration Word Low
  */
@@ -521,7 +528,7 @@
 #if defined(CONFIG_MPC834X)
 #define HRCWH_ROM_LOC_PCI2             0x00200000
 #endif
-#if defined(CONIFG_MPC837X)
+#if defined(CONFIG_MPC837X)
 #define HRCWH_ROM_LOC_ON_CHIP_ROM      0x00300000
 #endif
 #define HRCWH_ROM_LOC_LOCAL_8BIT       0x00500000
@@ -537,12 +544,14 @@
 #define HRCWH_RL_EXT_LEGACY            0x00000000
 #define HRCWH_RL_EXT_NAND              0x00040000
 
+#define HRCWH_TSEC1M_MASK              0x0000E000
 #define HRCWH_TSEC1M_IN_MII            0x00000000
 #define HRCWH_TSEC1M_IN_RMII           0x00002000
 #define HRCWH_TSEC1M_IN_RGMII          0x00006000
 #define HRCWH_TSEC1M_IN_RTBI           0x0000A000
 #define HRCWH_TSEC1M_IN_SGMII          0x0000C000
 
+#define HRCWH_TSEC2M_MASK              0x00001C00
 #define HRCWH_TSEC2M_IN_MII            0x00000000
 #define HRCWH_TSEC2M_IN_RMII           0x00000400
 #define HRCWH_TSEC2M_IN_RGMII          0x00000C00