Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / include / ns9750_mem.h

diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h
index 44c8ddcdd644e3ec46ebcef2661eb8b9a3429fed..666e4127c8f02ce1a3f45c4a16b705c290750046 100644 (file)
--- a/include/ns9750_mem.h
+++ b/include/ns9750_mem.h
@@ -35,23 +35,23 @@
 
 /* the register addresses */
 
-#define NS9750_MEM_CTRL                (0x0000)
-#define NS9750_MEM_STATUS              (0x0004)
-#define NS9750_MEM_CFG                 (0x0008)
-#define NS9750_MEM_DYN_CTRL            (0x0020)
-#define NS9750_MEM_DYN_REFRESH                 (0x0024)
+#define NS9750_MEM_CTRL                        (0x0000)
+#define NS9750_MEM_STATUS              (0x0004)
+#define NS9750_MEM_CFG                 (0x0008)
+#define NS9750_MEM_DYN_CTRL            (0x0020)
+#define NS9750_MEM_DYN_REFRESH         (0x0024)
 #define NS9750_MEM_DYN_READ_CFG                (0x0028)
-#define NS9750_MEM_DYN_TRP                     (0x0030)
-#define NS9750_MEM_DYN_TRAS                    (0x0034)
-#define NS9750_MEM_DYN_TSREX                   (0x0038)
-#define NS9750_MEM_DYN_TAPR            (0x003C)
-#define NS9750_MEM_DYN_TDAL                    (0x0040)
-#define NS9750_MEM_DYN_TWR                     (0x0044)
-#define NS9750_MEM_DYN_TRC                     (0x0048)
-#define NS9750_MEM_DYN_TRFC                    (0x004C)
-#define NS9750_MEM_DYN_TXSR                    (0x0050)
-#define NS9750_MEM_DYN_TRRD                    (0x0054)
-#define NS9750_MEM_DYN_TMRD                    (0x0058)
+#define NS9750_MEM_DYN_TRP             (0x0030)
+#define NS9750_MEM_DYN_TRAS            (0x0034)
+#define NS9750_MEM_DYN_TSREX           (0x0038)
+#define NS9750_MEM_DYN_TAPR            (0x003C)
+#define NS9750_MEM_DYN_TDAL            (0x0040)
+#define NS9750_MEM_DYN_TWR             (0x0044)
+#define NS9750_MEM_DYN_TRC             (0x0048)
+#define NS9750_MEM_DYN_TRFC            (0x004C)
+#define NS9750_MEM_DYN_TXSR            (0x0050)
+#define NS9750_MEM_DYN_TRRD            (0x0054)
+#define NS9750_MEM_DYN_TMRD            (0x0058)
 #define NS9750_MEM_STAT_EXT_WAIT       (0x0080)
 #define NS9750_MEM_DYN_CFG_BASE                (0x0100)
 #define NS9750_MEM_DYN_RAS_CAS_BASE    (0x0104)
@@ -102,7 +102,7 @@
 #define NS9750_MEM_DYN_REFRESH_MA      (0x000007FF)
 
 #define NS9750_MEM_DYN_READ_CFG_MA     (0x00000003)
-#define NS9750_MEM_DYN_READ_CFG_DELAY0         (0x00000001)
+#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001)
 #define NS9750_MEM_DYN_READ_CFG_DELAY1  (0x00000002)
 #define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003)
 
@@ -137,13 +137,13 @@
 #define NS9750_MEM_DYN_CFG_MD          (0x00000018)
 
 #define NS9750_MEM_DYN_RAS_CAS_CAS_MA  (0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_1   (0x00000100)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_2   (0x00000200)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_3   (0x00000300)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_1   (0x00000100)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_2   (0x00000200)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_3   (0x00000300)
 #define NS9750_MEM_DYN_RAS_CAS_RAS_MA  (0x00000003)
 #define NS9750_MEM_DYN_RAS_CAS_RAS_1   (0x00000001)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_2   (0x00000002)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_3   (0x00000003)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_2   (0x00000002)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_3   (0x00000003)
 
 #define NS9750_MEM_STAT_CFG_PSMC       (0x00100000)
 #define NS9750_MEM_STAT_CFG_BSMC       (0x00080000)
@@ -153,7 +153,7 @@
 #define NS9750_MEM_STAT_CFG_PM         (0x00000008)
 #define NS9750_MEM_STAT_CFG_MW_MA      (0x00000003)
 #define NS9750_MEM_STAT_CFG_MW_8       (0x00000000)
-#define NS9750_MEM_STAT_CFG_MW_16              (0x00000001)
+#define NS9750_MEM_STAT_CFG_MW_16      (0x00000001)
 #define NS9750_MEM_STAT_CFG_MW_32      (0x00000002)
 
 #define NS9750_MEM_STAT_WAIT_WEN_MA    (0x0000000F)