microblaze: ml401 - add ifdef for GPIO

[karo-tx-uboot.git] / include / ppc405.h

diff --git a/include/ppc405.h b/include/ppc405.h
index 2c5591726c3a2e5bda488a75fe973fa302203f79..37b121c3dcc17cc42b72b4b1206edc34e2832452 100644 (file)
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -118,7 +118,17 @@
 /******************************************************************************
  * Universal interrupt controller
  ******************************************************************************/
+#define UIC_SR 0x0                     /* UIC status                      */
+#define UIC_ER 0x2                     /* UIC enable                      */
+#define UIC_CR 0x3                     /* UIC critical                    */
+#define UIC_PR 0x4                     /* UIC polarity                    */
+#define UIC_TR 0x5                     /* UIC triggering                  */
+#define UIC_MSR 0x6                    /* UIC masked status               */
+#define UIC_VR 0x7                     /* UIC vector                      */
+#define UIC_VCR 0x8                    /* UIC vector configuration        */
+
 #define UIC_DCR_BASE 0xc0
+#define UIC0_DCR_BASE UIC_DCR_BASE
 #define uicsr        (UIC_DCR_BASE+0x0)  /* UIC status                       */
 #define uicsrs       (UIC_DCR_BASE+0x1)  /* UIC status set                   */
 #define uicer        (UIC_DCR_BASE+0x2)  /* UIC enable                       */
@@ -141,6 +151,7 @@
 #define uic0vcr       uicvcr           /* UIC vector configuration*/
 
 #define UIC_DCR_BASE1 0xd0
+#define UIC1_DCR_BASE 0xd0
 #define uic1sr        (UIC_DCR_BASE1+0x0)  /* UIC status            */
 #define uic1srs       (UIC_DCR_BASE1+0x1)  /* UIC status set        */
 #define uic1er        (UIC_DCR_BASE1+0x2)  /* UIC enable            */
@@ -152,6 +163,7 @@
 #define uic1vcr       (UIC_DCR_BASE1+0x8)  /* UIC vector configuration*/
 
 #define UIC_DCR_BASE2 0xe0
+#define UIC2_DCR_BASE 0xe0
 #define uic2sr        (UIC_DCR_BASE2+0x0)  /* UIC status            */
 #define uic2srs       (UIC_DCR_BASE2+0x1)  /* UIC status set        */
 #define uic2er        (UIC_DCR_BASE2+0x2)  /* UIC enable            */
@@ -237,10 +249,13 @@
 #define UIC_ENET1              0x00000040      /* */
 #define UIC_PCIEMSI2           0x00000020      /* */
 #define UIC_EIRQ4              0x00000010      /**/
-#define UIC_UIC2NC             0x00000008      /* */
-#define UIC_UIC2C              0x00000004      /* */
-#define UIC_UIC1NC             0x00000002      /* */
-#define UIC_UIC1C              0x00000001      /* */
+#define UICB0_UIC2NCI          0x00000008      /* */
+#define UICB0_UIC2CI           0x00000004      /* */
+#define UICB0_UIC1NCI          0x00000002      /* */
+#define UICB0_UIC1CI           0x00000001      /* */
+
+#define UICB0_ALL              (UICB0_UIC1CI | UICB0_UIC1NCI | \
+                                UICB0_UIC1CI | UICB0_UIC2NCI)
 
 #define UIC_MAL_TXEOB          UIC_MTE/* MAL TXEOB                          */
 #define UIC_MAL_RXEOB          UIC_MRE/* MAL RXEOB                          */
@@ -784,6 +799,14 @@
 #define reset   (CNTRL_DCR_BASE+0x3)  /* reset register                             */
 #define strap   (CNTRL_DCR_BASE+0x4)  /* strap register                             */
 
+#define CPC0_CR0  (CNTRL_DCR_BASE+0x1)  /* chip control register 0          */
+#define CPC0_CR1  (CNTRL_DCR_BASE+0x2)  /* chip control register 1          */
+#define CPC0_PSR  (CNTRL_DCR_BASE+0x4)  /* chip pin strapping register      */
+
+/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
+#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
+#define CPC0_ECR  (0xaa)               /* edge conditioner register */
+
 #define ecr     (0xaa)                /* edge conditioner register (405gpr)  */
 
 /* Bit definitions */
@@ -1135,6 +1158,8 @@
 
 #endif /* CONFIG_405EZ */
 
+#define GPIO0_BASE             GPIO_BASE
+
 #if defined(CONFIG_405EX)
 #define SDR0_SRST              0x0200
 
@@ -1572,6 +1597,19 @@
 #define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
 #define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
 #define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
+
+#define SDR0_PFC0              0x4100
+#define SDR0_PFC1              0x4101
+#define SDR0_PFC1_U1ME         0x02000000
+#define SDR0_PFC1_U0ME         0x00080000
+#define SDR0_PFC1_U0IM         0x00040000
+#define SDR0_PFC1_SIS          0x00020000
+#define SDR0_PFC1_DMAAEN       0x00010000
+#define SDR0_PFC1_DMADEN       0x00008000
+#define SDR0_PFC1_USBEN                0x00004000
+#define SDR0_PFC1_AHBSWAP      0x00000020
+#define SDR0_PFC1_USBBIGEN     0x00000010
+#define SDR0_PFC1_GPT_FREQ     0x0000000f
 #endif
 
 #endif /* __PPC405_H__ */