#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
/* Power Managment Receiver */
+#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
+#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
+#define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D
+#define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E
+#define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F
+#define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F
+#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61
+#define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62
+#define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63
+#define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64
+#define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65
+#define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66
+#define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67
+#define TWL4030_PM_RECEIVER_MISC_CFG 0x68
+#define TWL4030_PM_RECEIVER_LS_TST_A 0x69
+#define TWL4030_PM_RECEIVER_LS_TST_B 0x6A
+#define TWL4030_PM_RECEIVER_LS_TST_C 0x6B
+#define TWL4030_PM_RECEIVER_LS_TST_D 0x6C
+#define TWL4030_PM_RECEIVER_BB_CFG 0x6D
+#define TWL4030_PM_RECEIVER_MISC_TST 0x6E
+#define TWL4030_PM_RECEIVER_TRIM1 0x6F
+#define TWL4030_PM_RECEIVER_TRIM2 0x70
+#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71
+#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72
+#define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73
+#define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74
+#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75
+#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76
+#define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77
+#define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78
+#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79
+#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A
+#define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B
+#define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C
+#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D
+#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E
+#define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F
+#define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80
+#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81
+#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82
+#define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83
+#define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84
+#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85
+#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86
+#define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87
+#define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88
+#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89
+#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A
+#define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B
+#define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C
+#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D
+#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E
+#define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F
+#define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90
+#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91
+#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92
+#define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93
+#define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94
+#define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95
+#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96
+#define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97
+#define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98
+#define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99
+#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A
+#define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B
+#define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C
+#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D
+#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E
+#define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F
+#define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0
+#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1
+#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2
+#define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3
+#define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4
+#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5
+#define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6
+#define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7
+#define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8
+#define TWL4030_PM_RECEIVER_VIO_CFG 0xA9
+#define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA
+#define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB
+#define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC
+#define TWL4030_PM_RECEIVER_VIO_OSC 0xAD
+#define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE
+#define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF
+#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0
+#define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1
+#define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2
+#define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3
+#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4
+#define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5
+#define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6
+#define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7
+#define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8
+#define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9
+#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA
+#define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB
+#define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC
+#define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD
+#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE
+#define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF
+#define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0
+#define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1
+#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2
+#define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3
+#define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4
+#define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5
+#define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6
+#define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7
+#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8
+#define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9
+#define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA
+#define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB
#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC
#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD
#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE
#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3
#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4
#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5
-#define TWL4030_PM_RECEIVER_VUSBCP_DEV_TYPE 0xD6
-#define TWL4030_PM_RECEIVER_VUSBCP_DEV_REMAP 0xD7
+#define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6
+#define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7
#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8
#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9
+#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA
+#define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB
+#define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC
+#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD
+#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE
+#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF
+#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0
+#define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1
+#define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2
+#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3
+#define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4
+#define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5
+#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6
+#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7
+#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8
+#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9
+#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA
+#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB
+#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC
+#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED
+#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE
+#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF
+#define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
+#define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
+
+/* LED */
+#define TWL4030_LED_LEDEN 0xEE
/* Keypad */
#define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
return i2c_read(chip_no, reg, 1, val, 1);
}
+/*
+ * Power
+ */
+
+/* For hardware resetting */
+void twl4030_power_reset_init(void);
+/* For initializing power device */
+void twl4030_power_init(void);
+/* For initializing mmc power */
+void twl4030_power_mmc_init(void);
+
+/*
+ * LED
+ */
+void twl4030_led_init(void);
+
#endif /* TWL4030_H */
projects / karo-tx-uboot.git / blobdiff