fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0

[karo-tx-uboot.git] / include / usb / ehci-fsl.h

diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 734305b9dba25fd1e1809e96db81781da0ea1659..c9ee1d5bf6264b257f6042b348c20fa2f6de7606 100644 (file)
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -163,6 +163,13 @@
 #define CONFIG_SYS_FSL_USB2_ADDR       0
 #endif
 
+/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH           4
+
 /*
  * USB Registers
  */