if (core_clk > 800000000) {
div_core = 3;
- increase_core_voltage(true);
} else {
div_core = 2;
- increase_core_voltage(false);
+ }
+ ret = adjust_core_voltage(core_clk / 1000000);
+ if (ret) {
+ diag_printf("Failed to adjust core voltage for %u MHz\n",
+ core_clk / 1000000);
+ return ret;
}
cyg_hal_plf_serial_stop();