POST: preparations for moving CONFIG_POST to Makefiles

[karo-tx-uboot.git] / post / cpu / ppc4xx / cache_4xx.S

diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S
index dddd76b2355c8a62fa0e75f6614b721d3c53556c..455ffa072691108b85d9b1aae32b3ce55514638f 100644 (file)
--- a/post/cpu/ppc4xx/cache_4xx.S
+++ b/post/cpu/ppc4xx/cache_4xx.S
@@ -25,8 +25,6 @@
 
 #include <config.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
@@ -37,6 +35,13 @@
 
        .text
 
+       /*
+        * All 44x variants deal with cache management differently
+        * because they have the address translation always enabled.
+        * The 40x ppc's don't use address translation in U-Boot at all,
+        * so we have to distinguish here between 40x and 44x.
+        */
+#ifdef CONFIG_440
 /* void cache_post_disable (int tlb)
  */
 cache_post_disable:
@@ -68,6 +73,43 @@ cache_post_wb:
        sync
        isync
        blr
+#else
+/* void cache_post_disable (int tlb)
+ */
+cache_post_disable:
+       lis     r0, 0x0000
+       ori     r0, r0, 0x0000
+       mtdccr  r0
+       sync
+       isync
+       blr
+
+/* void cache_post_wt (int tlb)
+ */
+cache_post_wt:
+       lis     r0, 0x8000
+       ori     r0, r0, 0x0000
+       mtdccr  r0
+       lis     r0, 0x8000
+       ori     r0, r0, 0x0000
+       mtdcwr  r0
+       sync
+       isync
+       blr
+
+/* void cache_post_wb (int tlb)
+ */
+cache_post_wb:
+       lis     r0, 0x8000
+       ori     r0, r0, 0x0000
+       mtdccr  r0
+       lis     r0, 0x0000
+       ori     r0, r0, 0x0000
+       mtdcwr  r0
+       sync
+       isync
+       blr
+#endif
 
 /* void cache_post_dinvalidate (void *p, int size)
  */
@@ -445,4 +487,3 @@ cache_post_test_inst:
        blr
 
 #endif /* CONFIG_POST & CFG_POST_CACHE */
-#endif /* CONFIG_POST */