X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;ds=sidebyside;f=board%2Fatmel%2Fatngw100%2Fatngw100.c;h=dacd4278314c5b3ed0c0c10a44f0c951da621e3c;hb=d6ac3333c6974b4cb8bd1c34abd23817fb97f1af;hp=bd4b6b4ce5b8cabc90dbc5b8a635b74d70de7157;hpb=6b4439444286e0fcd01596df504e6ca897ad3e5a;p=karo-tx-uboot.git

diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
index bd4b6b4ce5..dacd427831 100644
--- a/board/atmel/atngw100/atngw100.c
+++ b/board/atmel/atngw100/atngw100.c
@@ -1,35 +1,37 @@
 /*
  * Copyright (C) 2006 Atmel Corporation
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 
 #include <asm/io.h>
 #include <asm/sdram.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix2.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct sdram_info sdram = {
-	.phys_addr	= CFG_SDRAM_BASE,
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+	{
+		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_NONE,
+	}, {
+		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
+					| MMU_VMR_CACHE_WRBACK,
+	},
+};
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_16BIT,
 	.row_bits	= 13,
 	.col_bits	= 9,
 	.bank_bits	= 2,
@@ -40,34 +42,68 @@ static const struct sdram_info sdram = {
 	.trcd		= 2,
 	.tras		= 5,
 	.txsr		= 5,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
 };
 
 int board_early_init_f(void)
 {
-	/* Set the SDRAM_ENABLE bit in the HEBI SFR */
-	hmatrix2_writel(SFR4, 1 << 1);
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
+	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
 
-	gpio_enable_ebi();
-	gpio_enable_usart1();
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
 
 #if defined(CONFIG_MACB)
-	gpio_enable_macb0();
-	gpio_enable_macb1();
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
 #endif
 #if defined(CONFIG_MMC)
-	gpio_enable_mmci();
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
 #endif
 
 	return 0;
 }
 
-long int initdram(int board_type)
+int board_early_init_r(void)
 {
-	return sdram_init(&sdram);
+	gd->bd->bi_phy_id[0] = 0x01;
+	gd->bd->bi_phy_id[1] = 0x03;
+	return 0;
 }
 
-void board_init_info(void)
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
 {
-	gd->bd->bi_phy_id[0] = 0x01;
-	gd->bd->bi_phy_id[1] = 0x03;
+	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
 }
+#endif /* CONFIG_ATMEL_SPI */