X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;ds=sidebyside;f=include%2Fmiiphy.h;h=fa33ec7f71d5a70b053f383534805db896e8ea3d;hb=d43bc3d2d09022bcffa1302b8f51e7fabe2dc68a;hp=7f61cfa4e37f8677de48cdb4f95d37d646d4aea2;hpb=855a496fe9ba431772f1ff1aef21a5c001288bb0;p=karo-tx-uboot.git

diff --git a/include/miiphy.h b/include/miiphy.h
index 7f61cfa4e3..fa33ec7f71 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -1,4 +1,6 @@
 /*----------------------------------------------------------------------------+
+|   This source code is dual-licensed.  You may use it under the terms of the
+|   GNU General Public License version 2, or under the license below.
 |
 |	This source code has been made available to you by IBM on an AS-IS
 |	basis.	Anyone receiving this source is licensed under IBM
@@ -26,34 +28,49 @@
 |
 |  Author:	Mark Wisner
 |
-|  Change Activity-
-|
-|  Date	       Description of Change					BY
-|  ---------   ---------------------					---
-|  04-May-99   Created							MKW
-|  07-Jul-99   Added full duplex support				MKW
-|  08-Sep-01   Tweaks							gvb
-|
 +----------------------------------------------------------------------------*/
 #ifndef _miiphy_h_
 #define _miiphy_h_
 
+#include <net.h>
 
-int  miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value);
-int  miiphy_write(unsigned char addr, unsigned char reg, unsigned short value);
-int  miiphy_info(unsigned char addr, unsigned int  *oui, unsigned char *model,
-		 unsigned char *rev);
-int  miiphy_reset(unsigned char addr);
-int  miiphy_speed(unsigned char addr);
-int  miiphy_duplex(unsigned char addr);
-#ifdef CFG_FAULT_ECHO_LINK_DOWN
-int  miiphy_link(unsigned char addr);
+int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
+		 unsigned short *value);
+int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
+		  unsigned short value);
+int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
+		 unsigned char *model, unsigned char *rev);
+int miiphy_reset (char *devname, unsigned char addr);
+int miiphy_speed (char *devname, unsigned char addr);
+int miiphy_duplex (char *devname, unsigned char addr);
+int miiphy_is_1000base_x (char *devname, unsigned char addr);
+#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+int miiphy_link (char *devname, unsigned char addr);
 #endif
 
+void miiphy_init (void);
+
+void miiphy_register (char *devname,
+		      int (*read) (char *devname, unsigned char addr,
+				   unsigned char reg, unsigned short *value),
+		      int (*write) (char *devname, unsigned char addr,
+				    unsigned char reg, unsigned short value));
+
+int miiphy_set_current_dev (char *devname);
+char *miiphy_get_current_dev (void);
+
+void miiphy_listdev (void);
+
+#define BB_MII_DEVNAME	"bbmii"
+
+int bb_miiphy_read (char *devname, unsigned char addr,
+		    unsigned char reg, unsigned short *value);
+int bb_miiphy_write (char *devname, unsigned char addr,
+		     unsigned char reg, unsigned short value);
 
 /* phy seed setup */
 #define AUTO			99
-#define _1000BASET              1000
+#define _1000BASET		1000
 #define _100BASET		100
 #define _10BASET		10
 #define HALF			22
@@ -68,9 +85,10 @@ int  miiphy_link(unsigned char addr);
 #define PHY_ANLPAR		0x05
 #define PHY_ANER		0x06
 #define PHY_ANNPTR		0x07
-#define PHY_ANLPNP              0x08
-#define PHY_1000BTCR            0x09
-#define PHY_1000BTSR            0x0A
+#define PHY_ANLPNP		0x08
+#define PHY_1000BTCR		0x09
+#define PHY_1000BTSR		0x0A
+#define PHY_EXSR		0x0F
 #define PHY_PHYSTS		0x10
 #define PHY_MIPSCR		0x11
 #define PHY_MIPGSR		0x12
@@ -93,12 +111,18 @@ int  miiphy_link(unsigned char addr);
 #define PHY_BMCR_DPLX		0x0100
 #define PHY_BMCR_COL_TST	0x0080
 
+#define PHY_BMCR_SPEED_MASK	0x2040
+#define PHY_BMCR_1000_MBPS	0x0040
+#define PHY_BMCR_100_MBPS	0x2000
+#define PHY_BMCR_10_MBPS	0x0000
+
 /* phy BMSR */
 #define PHY_BMSR_100T4		0x8000
 #define PHY_BMSR_100TXF		0x4000
 #define PHY_BMSR_100TXH		0x2000
 #define PHY_BMSR_10TF		0x1000
 #define PHY_BMSR_10TH		0x0800
+#define PHY_BMSR_EXT_STAT	0x0100
 #define PHY_BMSR_PRE_SUP	0x0040
 #define PHY_BMSR_AUTN_COMP	0x0020
 #define PHY_BMSR_RF		0x0010
@@ -111,19 +135,42 @@ int  miiphy_link(unsigned char addr);
 #define PHY_ANLPAR_NP		0x8000
 #define PHY_ANLPAR_ACK		0x4000
 #define PHY_ANLPAR_RF		0x2000
+#define PHY_ANLPAR_ASYMP	0x0800
+#define PHY_ANLPAR_PAUSE	0x0400
 #define PHY_ANLPAR_T4		0x0200
 #define PHY_ANLPAR_TXFD		0x0100
 #define PHY_ANLPAR_TX		0x0080
 #define PHY_ANLPAR_10FD		0x0040
 #define PHY_ANLPAR_10		0x0020
-#define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */
-
-/* PHY_1000BTSR */
-#define PHY_1000BTSR_MSCF       0x8000
-#define PHY_1000BTSR_MSCR       0x4000
-#define PHY_1000BTSR_LRS        0x2000
-#define PHY_1000BTSR_RRS        0x1000
-#define PHY_1000BTSR_1000FD     0x0800
-#define PHY_1000BTSR_1000HD     0x0400
+#define PHY_ANLPAR_100		0x0380	/* we can run at 100 */
+/* phy ANLPAR 1000BASE-X */
+#define PHY_X_ANLPAR_NP		0x8000
+#define PHY_X_ANLPAR_ACK	0x4000
+#define PHY_X_ANLPAR_RF_MASK	0x3000
+#define PHY_X_ANLPAR_PAUSE_MASK	0x0180
+#define PHY_X_ANLPAR_HD		0x0040
+#define PHY_X_ANLPAR_FD		0x0020
+
+#define PHY_ANLPAR_PSB_MASK	0x001f
+#define PHY_ANLPAR_PSB_802_3	0x0001
+#define PHY_ANLPAR_PSB_802_9	0x0002
+
+/* phy 1000BTCR */
+#define PHY_1000BTCR_1000FD	0x0200
+#define PHY_1000BTCR_1000HD	0x0100
+
+/* phy 1000BTSR */
+#define PHY_1000BTSR_MSCF	0x8000
+#define PHY_1000BTSR_MSCR	0x4000
+#define PHY_1000BTSR_LRS	0x2000
+#define PHY_1000BTSR_RRS	0x1000
+#define PHY_1000BTSR_1000FD	0x0800
+#define PHY_1000BTSR_1000HD	0x0400
+
+/* phy EXSR */
+#define PHY_EXSR_1000XF		0x8000
+#define PHY_EXSR_1000XH		0x4000
+#define PHY_EXSR_1000TF		0x2000
+#define PHY_EXSR_1000TH		0x1000
 
 #endif