X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=README;h=c6b179cb627217e63d5b6967ce88651211538697;hb=96d21237ec2b799f60a827ea680594b7ebfdac7f;hp=0491b1109a265c77b6734176a1700628b53d77d2;hpb=f38536f9138c253b0c1f9c72093a7ec6808e638f;p=karo-tx-uboot.git diff --git a/README b/README index 0491b1109a..c6b179cb62 100644 --- a/README +++ b/README @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 - 2009 +# (C) Copyright 2000 - 2011 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -147,7 +147,7 @@ Directory Hierarchy: /cpu CPU specific files /arm720t Files specific to ARM 720 CPUs /arm920t Files specific to ARM 920 CPUs - /at91rm9200 Files specific to Atmel AT91RM9200 CPU + /at91 Files specific to Atmel AT91RM9200 CPU /imx Files specific to Freescale MC9328 i.MX CPUs /s3c24x0 Files specific to Samsung S3C24X0 CPUs /arm925t Files specific to ARM 925 CPUs @@ -180,6 +180,12 @@ Directory Hierarchy: /lib Architecture specific library files /mips Files generic to MIPS architecture /cpu CPU specific files + /mips32 Files specific to MIPS32 CPUs + /xburst Files specific to Ingenic XBurst CPUs + /lib Architecture specific library files + /nds32 Files generic to NDS32 architecture + /cpu CPU specific files + /n1213 Files specific to Andes Technology N1213 CPUs /lib Architecture specific library files /nios2 Files generic to Altera NIOS2 architecture /cpu CPU specific files @@ -356,6 +362,18 @@ The following options need to be configured: Define this option if you want to enable the ICache only when Code runs from RAM. +- 85xx CPU Options: + CONFIG_SYS_FSL_TBCLK_DIV + + Defines the core time base clock divider ratio compared to the + system clock. On most PQ3 devices this is 8, on newer QorIQ + devices it can be 16 or 32. The ratio varies from SoC to Soc. + + CONFIG_SYS_FSL_PCIE_COMPAT + + Defines the string to utilize when trying to match PCIe device + tree nodes for the given platform. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO @@ -370,6 +388,38 @@ The following options need to be configured: 2. The core frequency as calculated above is multiplied by this value. +- MIPS CPU options: + CONFIG_SYS_INIT_SP_OFFSET + + Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack + pointer. This is needed for the temporary stack before + relocation. + + CONFIG_SYS_MIPS_CACHE_MODE + + Cache operation mode for the MIPS CPU. + See also arch/mips/include/asm/mipsregs.h. + Possible values are: + CONF_CM_CACHABLE_NO_WA + CONF_CM_CACHABLE_WA + CONF_CM_UNCACHED + CONF_CM_CACHABLE_NONCOHERENT + CONF_CM_CACHABLE_CE + CONF_CM_CACHABLE_COW + CONF_CM_CACHABLE_CUW + CONF_CM_CACHABLE_ACCELERATED + + CONFIG_SYS_XWAY_EBU_BOOTCFG + + Special option for Lantiq XWAY SoCs for booting from NOR flash. + See also arch/mips/cpu/mips32/start.S. + + CONFIG_XWAY_SWAP_BYTES + + Enable compilation of tools/xway-swap-bytes needed for Lantiq + XWAY SoCs for booting from NOR flash. The U-Boot image needs to + be swapped if a flash programmer is used. + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ @@ -430,6 +480,16 @@ The following options need to be configured: crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. + CONFIG_MACH_TYPE [relevant for ARM only][mandatory] + + This setting is mandatory for all boards that have only one + machine type and must be used to specify the machine type + number as it appears in the ARM machine registry + (see http://www.arm.linux.org.uk/developer/machines/). + Only boards that have multiple machine types supported + in a single configuration file and the machine type is + runtime discoverable, do not have to use this setting. + - vxWorks boot parameters: bootvx constructs a valid bootline using the following @@ -448,6 +508,17 @@ The following options need to be configured: Note: If a "bootargs" environment is defined, it will overwride the defaults discussed just above. +- Cache Configuration: + CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot + CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot + CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot + +- Cache Configuration for ARM: + CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache + controller + CONFIG_SYS_PL310_BASE - Physical base address of PL310 + controller register space + - Serial Ports: CONFIG_PL010_SERIAL @@ -468,6 +539,18 @@ The following options need to be configured: define this to a list of base addresses for each (supported) port. See e.g. include/configs/versatile.h + CONFIG_PL011_SERIAL_RLCR + + Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) + have separate receive and transmit line control registers. Set + this variable to initialize the extra register. + + CONFIG_PL011_SERIAL_FLUSH_ON_INIT + + On some platforms (e.g. U8500) U-Boot is loaded by a second stage + boot loader that has already initialized the UART. Define this + variable to flush the UART at init time. + - Console Interface: Depending on board, define exactly one serial port @@ -541,6 +624,20 @@ The following options need to be configured: must be defined, to setup the maximum idle timeout for the SMC. +- Pre-Console Buffer: + Prior to the console being initialised (i.e. serial UART + initialised etc) all console output is silently discarded. + Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to + buffer any console messages prior to the console being + initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ + bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is + a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ + bytes are output before the console is initialised, the + earlier bytes are discarded. + + 'Sane' compilers will generate smaller code if + CONFIG_PRE_CON_BUF_SZ is a power of 2 + - Boot Delay: CONFIG_BOOTDELAY - in seconds Delay before automatically booting the default image; set to -1 to disable autoboot. @@ -646,6 +743,7 @@ The following options need to be configured: CONFIG_CMD_FLASH flinfo, erase, protect CONFIG_CMD_FPGA FPGA device initialization support CONFIG_CMD_GO * the 'go' command (exec code) + CONFIG_CMD_GREPENV * search environment CONFIG_CMD_HWFLOW * RTS/CTS hw flow control CONFIG_CMD_I2C * I2C serial bus support CONFIG_CMD_IDE * IDE harddisk support @@ -689,8 +787,9 @@ The following options need to be configured: (requires CONFIG_CMD_MEMORY) CONFIG_CMD_SOURCE "source" command Support CONFIG_CMD_SPI * SPI serial bus support + CONFIG_CMD_TFTPSRV * TFTP transfer in server mode + CONFIG_CMD_TIME * run command and report execution time CONFIG_CMD_USB * USB support - CONFIG_CMD_VFD * VFD support (TRAB) CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_FSL * Microblaze FSL support @@ -719,10 +818,17 @@ The following options need to be configured: - Watchdog: CONFIG_WATCHDOG If this variable is defined, it enables watchdog - support. There must be support in the platform specific - code for a watchdog. For the 8xx and 8260 CPUs, the - SIU Watchdog feature is enabled in the SYPCR - register. + support for the SoC. There must be support in the SoC + specific code for a watchdog. For the 8xx and 8260 + CPUs, the SIU Watchdog feature is enabled in the SYPCR + register. When supported for a specific SoC is + available, then no further board specific code should + be needed to use it. + + CONFIG_HW_WATCHDOG + When using a watchdog circuitry external to the used + SoC, then define this variable and provide board + specific code for the "hw_watchdog_reset" function. - U-Boot Version: CONFIG_VERSION_VARIABLE @@ -1011,6 +1117,15 @@ The following options need to be configured: enabled with CONFIG_CMD_MMC. The MMC driver also works with the FAT fs. This is enabled with CONFIG_CMD_FAT. + CONFIG_SH_MMCIF + Support for Renesas on-chip MMCIF controller + + CONFIG_SH_MMCIF_ADDR + Define the base address of MMCIF registers + + CONFIG_SH_MMCIF_CLK + Define the clock frequency for MMCIF + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV @@ -1082,7 +1197,7 @@ The following options need to be configured: or CONFIG_VIDEO_SED13806_16BPP CONFIG_FSL_DIU_FB - Enable the Freescale DIU video driver. Reference boards for + Enable the Freescale DIU video driver. Reference boards for SOCs that have a DIU should define this macro to enable DIU support, and should also define these other macros: @@ -1095,13 +1210,10 @@ The following options need to be configured: CONFIG_VIDEO_LOGO CONFIG_VIDEO_BMP_LOGO - The DIU driver will look for the 'monitor' environment variable, - and if defined, enable the DIU as a console during boot. This - variable should be set to one of these values: - - '0' Output video to the DVI connector - '1' Output video to the LVDS connector - '2' Output video to the Dual-Link LVDS connector + The DIU driver will look for the 'video-mode' environment + variable, and if defined, enable the DIU as a console during + boot. See the documentation file README.video for a + description of this variable. - Keyboard Support: CONFIG_KEYBOARD @@ -1305,7 +1417,6 @@ The following options need to be configured: driver in use must provide a function: mcast() to join/leave a multicast group. - CONFIG_BOOTP_RANDOM_DELAY - BOOTP Recovery Mode: CONFIG_BOOTP_RANDOM_DELAY @@ -1665,12 +1776,12 @@ The following options need to be configured: => If you now switch to the new I2C Bus 3 with "i2c dev 3" - u-boot sends First the Commando to the mux@70 to enable - channel 6, and then the Commando to the mux@71 to enable + u-boot first sends the command to the mux@70 to enable + channel 6, and then the command to the mux@71 to enable the channel 4. After that, you can use the "normal" i2c commands as - usual, to communicate with your I2C devices behind + usual to communicate with your I2C devices behind the 2 muxes. This option is actually implemented for the bitbanging @@ -2003,28 +2114,6 @@ The following options need to be configured: example, some LED's) on your board. At the moment, the following checkpoints are implemented: -- Standalone program support: - CONFIG_STANDALONE_LOAD_ADDR - - This option allows to define board specific values - for the address where standalone program gets loaded, - thus overwriting the architecutre dependent default - settings. - -- Frame Buffer Address: - CONFIG_FB_ADDR - - Define CONFIG_FB_ADDR if you want to use specific address for - frame buffer. - Then system will reserve the frame buffer address to defined address - instead of lcd_setmem (this function grab the memory for frame buffer - by panel's size). - - Please see board_init_f function. - - If you want this config option then, - please define it at your board config file - Legacy uImage format: Arg Where When @@ -2178,6 +2267,25 @@ FIT uImage format: -150 common/cmd_nand.c Incorrect FIT image format 151 common/cmd_nand.c FIT image format OK +- Standalone program support: + CONFIG_STANDALONE_LOAD_ADDR + + This option defines a board specific value for the + address where standalone program gets loaded, thus + overwriting the architecture dependent default + settings. + +- Frame Buffer Address: + CONFIG_FB_ADDR + + Define CONFIG_FB_ADDR if you want to use specific + address for frame buffer. + Then system will reserve the frame buffer address to + defined address instead of lcd_setmem (this function + grabs the memory for frame buffer by panel's size). + + Please see board_init_f function. + - Automatic software updates via TFTP server CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP_CNT_MAX @@ -2197,11 +2305,50 @@ FIT uImage format: Adds the MTD partitioning infrastructure from the Linux kernel. Needed for UBI support. +- SPL framework + CONFIG_SPL + Enable building of SPL globally. + + CONFIG_SPL_TEXT_BASE + TEXT_BASE for linking the SPL binary. + + CONFIG_SPL_LDSCRIPT + LDSCRIPT for linking the SPL binary. + + CONFIG_SPL_LIBCOMMON_SUPPORT + Support for common/libcommon.o in SPL binary + + CONFIG_SPL_LIBDISK_SUPPORT + Support for disk/libdisk.o in SPL binary + + CONFIG_SPL_I2C_SUPPORT + Support for drivers/i2c/libi2c.o in SPL binary + + CONFIG_SPL_GPIO_SUPPORT + Support for drivers/gpio/libgpio.o in SPL binary + + CONFIG_SPL_MMC_SUPPORT + Support for drivers/mmc/libmmc.o in SPL binary + + CONFIG_SPL_SERIAL_SUPPORT + Support for drivers/serial/libserial.o in SPL binary + + CONFIG_SPL_SPI_FLASH_SUPPORT + Support for drivers/mtd/spi/libspi_flash.o in SPL binary + + CONFIG_SPL_SPI_SUPPORT + Support for drivers/spi/libspi.o in SPL binary + + CONFIG_SPL_FAT_SUPPORT + Support for fs/fat/libfat.o in SPL binary + + CONFIG_SPL_LIBGENERIC_SUPPORT + Support for lib/libgeneric.o in SPL binary Modem Support: -------------- -[so far only for SMDK2400 and TRAB boards] +[so far only for SMDK2400 boards] - Modem support enable: CONFIG_MODEM_SUPPORT @@ -2466,6 +2613,11 @@ The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: +- CONFIG_BUILD_ENVCRC: + + Builds up envcrc with the target environment so that external utils + may easily extract it and embed it in final U-Boot images. + - CONFIG_ENV_IS_IN_FLASH: Define this if the environment is in flash memory. @@ -2727,6 +2879,43 @@ Low Level (hardware related) configuration options: and RPXsuper) to be able to adjust the position of the IMMR register after a reset. +- CONFIG_SYS_CCSRBAR_DEFAULT: + Default (power-on reset) physical address of CCSR on Freescale + PowerPC SOCs. + +- CONFIG_SYS_CCSRBAR: + Virtual address of CCSR. On a 32-bit build, this is typically + the same value as CONFIG_SYS_CCSRBAR_DEFAULT. + + CONFIG_SYS_DEFAULT_IMMR must also be set to this value, + for cross-platform code that uses that macro instead. + +- CONFIG_SYS_CCSRBAR_PHYS: + Physical address of CCSR. CCSR can be relocated to a new + physical address, if desired. In this case, this macro should + be set to that address. Otherwise, it should be set to the + same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR + is typically relocated on 36-bit builds. It is recommended + that this macro be defined via the _HIGH and _LOW macros: + + #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH + * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) + +- CONFIG_SYS_CCSRBAR_PHYS_HIGH: + Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically + either 0 (32-bit build) or 0xF (36-bit build). This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSRBAR_PHYS_LOW: + Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSR_DO_NOT_RELOCATE: + If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be + forced to a value that ensures that CCSR is not relocated. + - Floppy Disk Support: CONFIG_SYS_FDC_DRIVE_NUMBER @@ -2753,6 +2942,14 @@ Low Level (hardware related) configuration options: source code. It is used to make hardware dependant initializations. +- CONFIG_IDE_AHB: + Most IDE controllers were designed to be connected with PCI + interface. Only few of them were designed for AHB interface. + When software is doing ATA command and data transfer to + IDE devices through IDE-AHB controller, some additional + registers accessing to these kind of IDE-AHB controller + is requierd. + - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx/82xx systems only] @@ -2881,6 +3078,14 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_SRIOn_MEM_SIZE: Size of SRIO port 'n' memory region +- CONFIG_SYS_NDFC_16 + Defined to tell the NDFC that the NAND chip is using a + 16 bit bus. + +- CONFIG_SYS_NDFC_EBC0_CFG + Sets the EBC0_CFG register for the NDFC. If not defined + a default value will be used. + - CONFIG_SPD_EEPROM Get DDR timing information from an I2C EEPROM. Common with pluggable memory modules such as SODIMMs @@ -2893,6 +3098,15 @@ Low Level (hardware related) configuration options: one, specify here. Note that the value must resolve to something your driver can deal with. +- CONFIG_SYS_DDR_RAW_TIMING + Get DDR timing information from other than SPD. Common with + soldered DDR chips onboard without SPD. DDR raw timing + parameters are extracted from datasheet and hard-coded into + header files or board specific files. + +- CONFIG_FSL_DDR_INTERACTIVE + Enable interactive DDR debugging. See doc/README.fsl-ddr. + - CONFIG_SYS_83XX_DDR_USES_CS0 Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. @@ -2946,7 +3160,7 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEM). - CONFIG_SKIP_LOWLEVEL_INIT - [ARM only] If this variable is defined, then certain + [ARM, NDS32, MIPS only] If this variable is defined, then certain low level initializations (like setting up the memory controller) are omitted and/or U-Boot does not relocate itself into RAM. @@ -2956,7 +3170,7 @@ Low Level (hardware related) configuration options: other boot loader or by a debugger which performs these initializations itself. -- CONFIG_PRELOADER +- CONFIG_SPL_BUILD Modifies the behaviour of start.S when compiling a loader that is executed before the actual U-Boot. E.g. when compiling a NAND SPL. @@ -3244,6 +3458,15 @@ List of environment variables (most likely not complete): This can be used to load and uncompress arbitrary data. + fdt_high - if set this restricts the maximum address that the + flattened device tree will be copied into upon boot. + If this is set to the special value 0xFFFFFFFF then + the fdt will not be copied at all on boot. For this + to work it must reside in writable memory, have + sufficient padding on the end of it for u-boot to + add the information it needs into it, and the memory + must be accessible by the kernel. + i2cfast - (PPC405GP|PPC405EP only) if set to 'y' configures Linux I2C driver for fast mode (400kHZ). This environment variable is used in @@ -3294,12 +3517,10 @@ List of environment variables (most likely not complete): bootstopkey - see CONFIG_AUTOBOOT_STOP_STR - ethprime - When CONFIG_NET_MULTI is enabled controls which - interface is used first. + ethprime - controls which interface is used first. - ethact - When CONFIG_NET_MULTI is enabled controls which - interface is currently active. For example you - can do the following + ethact - controls which interface is currently active. + For example you can do the following => setenv ethact FEC => ping 192.168.0.1 # traffic sent on FEC @@ -3341,6 +3562,25 @@ List of environment variables (most likely not complete): Ethernet is encapsulated/received over 802.1q VLAN tagged frames. +The following image location variables contain the location of images +used in booting. The "Image" column gives the role of the image and is +not an environment variable name. The other columns are environment +variable names. "File Name" gives the name of the file on a TFTP +server, "RAM Address" gives the location in RAM the image will be +loaded to, and "Flash Location" gives the image's address in NOR +flash or offset in NAND flash. + +*Note* - these variables don't have to be defined for all boards, some +boards currenlty use other variables for these purposes, and some +boards use these variables for other purposes. + +Image File Name RAM Address Flash Location +----- --------- ----------- -------------- +u-boot u-boot u-boot_addr_r u-boot_addr +Linux kernel bootfile kernel_addr_r kernel_addr +device tree blob fdtfile fdt_addr_r fdt_addr +ramdisk ramdiskfile ramdisk_addr_r ramdisk_addr + The following environment variables may be used and automatically updated by the network boot commands ("bootp" and "rarpboot"), depending the information provided by your boot server: @@ -3487,8 +3727,8 @@ details; basically, the header defines the following image properties: Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS, INTEGRITY). * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, - IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; - Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC). + IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; + Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC). * Compression Type (uncompressed, gzip, bzip2) * Load Address * Entry Point @@ -4181,6 +4421,20 @@ On Nios II, the ABI is documented here: Note: on Nios II, we give "-G0" option to gcc and don't use gp to access small data sections, so gp is free. +On NDS32, the following registers are used: + + R0-R1: argument/return + R2-R5: argument + R15: temporary register for assembler + R16: trampoline register + R28: frame pointer (FP) + R29: global pointer (GP) + R30: link register (LP) + R31: stack pointer (SP) + PC: program counter (PC) + + ==> U-Boot will use R10 to hold a pointer to the global data + NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope, or current versions of GCC may "optimize" the code too much. @@ -4346,9 +4600,7 @@ Coding Standards: All contributions to U-Boot should conform to the Linux kernel coding style; see the file "Documentation/CodingStyle" and the script -"scripts/Lindent" in your Linux kernel source directory. In sources -originating from U-Boot a style corresponding to "Lindent -pcs" (adding -spaces before parameters to function calls) is actually used. +"scripts/Lindent" in your Linux kernel source directory. Source files originating from a different project (for example the MTD subsystem) are generally exempt from these guidelines and are not @@ -4361,9 +4613,9 @@ in your code. Please also stick to the following formatting rules: - remove any trailing white space -- use TAB characters for indentation, not spaces +- use TAB characters for indentation and vertical alignment, not spaces - make sure NOT to use DOS '\r\n' line feeds -- do not add more than 2 empty lines to source files +- do not add more than 2 consecutive empty lines to source files - do not add trailing empty lines to source files Submissions which do not conform to the standards may be returned @@ -4397,14 +4649,14 @@ it: * For major contributions, your entry to the CREDITS file * When you add support for a new board, don't forget to add this - board to the MAKEALL script, too. + board to the MAINTAINERS file, too. * If your patch adds new configuration options, don't forget to document these in the README file. * The patch itself. If you are using git (which is *strongly* recommended) you can easily generate the patch using the - "git-format-patch". If you then use "git-send-email" to send it to + "git format-patch". If you then use "git send-email" to send it to the U-Boot mailing list, you will avoid most of the common problems with some other mail clients.