X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fcache_v7.c;h=4a6207a74064e3f7b3febb0c40249604378414b0;hb=b21a8dc446db69848aea810385e09020359de1d9;hp=f7865bc389c44d893f4d24137dcb1e25812ecb45;hpb=778c3cbd857f4abe54773f399204dd86ffe6516c;p=karo-tx-uboot.git diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index f7865bc389..4a6207a740 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -21,7 +21,8 @@ * to get size details from Current Cache Size ID Register(CCSIDR) */ static void set_csselr(u32 level, u32 type) -{ u32 csselr = level << 1 | type; +{ + u32 csselr = level << 1 | type; /* Write to Cache Size Selection Register(CSSELR) */ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); @@ -49,7 +50,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -66,14 +68,15 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, u32 num_ways, u32 way_shift, u32 log2_line_len) { - int way, set, setway; + int way, set; + u32 setway; /* * For optimal assembly code: @@ -93,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -134,7 +137,6 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation) static void v7_maint_dcache_all(u32 operation) { u32 level, cache_type, level_start_bit = 0; - u32 clidr = get_clidr(); for (level = 0; level < 7; level++) { @@ -147,8 +149,7 @@ static void v7_maint_dcache_all(u32 operation) } } -static void v7_dcache_clean_inval_range(u32 start, - u32 stop, u32 line_len) +static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) { u32 mva; @@ -214,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } /* Invalidate TLB */ @@ -227,11 +228,11 @@ static void v7_inval_tlb(void) "mcr p15, 0, %0, c8, c6, 0\n" /* Invalidate entire instruction TLB */ "mcr p15, 0, %0, c8, c5, 0\n" - /* Full system DSB - make sure that the invalidation is complete */ - "mcr p15, 0, %0, c7, c10, 4\n" - /* Full system ISB - make sure the instruction stream sees it */ - "mcr p15, 0, %0, c7, c5, 4\n" : : "r" (0)); + /* Full system DSB - make sure that the invalidation is complete */ + DSB; + /* Full system ISB - make sure the instruction stream sees it */ + ISB; } void invalidate_dcache_all(void) @@ -258,7 +259,6 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); @@ -288,15 +288,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) flush_dcache_range(start, stop); v7_inval_tlb(); } - -/* - * Flush range from all levels of d-cache/unified-cache used: - * Affects the range [start, start + size - 1] - */ -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) { @@ -306,22 +297,10 @@ void flush_dcache_all(void) { } -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ -} - -void flush_dcache_range(unsigned long start, unsigned long stop) -{ -} - void arm_init_before_mmu(void) { } -void flush_cache(unsigned long start, unsigned long size) -{ -} - void mmu_page_table_flush(unsigned long start, unsigned long stop) { } @@ -335,19 +314,23 @@ void arm_init_domains(void) /* Invalidate entire I-cache and branch predictor array */ void invalidate_icache_all(void) { - /* - * Invalidate all instruction caches to PoU. - * Also flushes branch target cache. - */ asm volatile ( + /* + * Invalidate all instruction caches to PoU. + * Also flushes branch target cache. + */ "mcr p15, 0, %0, c7, c5, 0\n" + /* Invalidate entire branch predictor array */ "mcr p15, 0, %0, c7, c5, 6\n" - /* Full system DSB - make sure that the invalidation is complete */ - "mcr p15, 0, %0, c7, c10, 4\n" - /* ISB - make sure the instruction stream sees it */ - "mcr p15, 0, %0, c7, c5, 4\n" + : : "r" (0)); + + /* Full system DSB - make sure that the invalidation is complete */ + DSB; + + /* ISB - make sure the instruction stream sees it */ + ISB; } #else void invalidate_icache_all(void) @@ -355,41 +338,10 @@ void invalidate_icache_all(void) } #endif -/* - * Stub implementations for outer cache operations - */ -void __v7_outer_cache_enable(void) -{ -} -void v7_outer_cache_enable(void) - __attribute__((weak, alias("__v7_outer_cache_enable"))); - -void __v7_outer_cache_disable(void) -{ -} -void v7_outer_cache_disable(void) - __attribute__((weak, alias("__v7_outer_cache_disable"))); - -void __v7_outer_cache_flush_all(void) -{ -} -void v7_outer_cache_flush_all(void) - __attribute__((weak, alias("__v7_outer_cache_flush_all"))); - -void __v7_outer_cache_inval_all(void) -{ -} -void v7_outer_cache_inval_all(void) - __attribute__((weak, alias("__v7_outer_cache_inval_all"))); - -void __v7_outer_cache_flush_range(u32 start, u32 end) -{ -} -void v7_outer_cache_flush_range(u32 start, u32 end) - __attribute__((weak, alias("__v7_outer_cache_flush_range"))); - -void __v7_outer_cache_inval_range(u32 start, u32 end) -{ -} -void v7_outer_cache_inval_range(u32 start, u32 end) - __attribute__((weak, alias("__v7_outer_cache_inval_range"))); +/* Stub implementations for outer cache operations */ +__weak void v7_outer_cache_enable(void) {} +__weak void v7_outer_cache_disable(void) {} +__weak void v7_outer_cache_flush_all(void) {} +__weak void v7_outer_cache_inval_all(void) {} +__weak void v7_outer_cache_flush_range(u32 start, u32 end) {} +__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}