X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mxs%2Fregs-ssp.h;h=b37e9b1e27b71eaf216f12f136211cb3c9475976;hb=3d5920a31bb846249385e1ca5c086662c39bc44e;hp=cf52a28c3becf83b79f7e74dc0da602784dc40db;hpb=7cdcaef0b286fa20926d750304442ad770a1fca8;p=karo-tx-uboot.git diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index cf52a28c3b..b37e9b1e27 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -6,52 +6,104 @@ * Based on code from LTIB: * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MX28_REGS_SSP_H__ #define __MX28_REGS_SSP_H__ -#include +#include #ifndef __ASSEMBLY__ +#if defined(CONFIG_SOC_MX23) +struct mxs_ssp_regs { + mxs_reg_32(hw_ssp_ctrl0); + mxs_reg_32(hw_ssp_cmd0); + mxs_reg_32(hw_ssp_cmd1); + mxs_reg_32(hw_ssp_compref); + mxs_reg_32(hw_ssp_compmask); + mxs_reg_32(hw_ssp_timing); + mxs_reg_32(hw_ssp_ctrl1); + mxs_reg_32(hw_ssp_data); + mxs_reg_32(hw_ssp_sdresp0); + mxs_reg_32(hw_ssp_sdresp1); + mxs_reg_32(hw_ssp_sdresp2); + mxs_reg_32(hw_ssp_sdresp3); + mxs_reg_32(hw_ssp_status); + reg_32(reserved[3]); + mxs_reg_32(hw_ssp_debug); + mxs_reg_32(hw_ssp_version); +}; +#elif defined(CONFIG_SOC_MX28) struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_xfer_size) - mxs_reg_32(hw_ssp_block_size) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_ddr_ctrl) - mxs_reg_32(hw_ssp_dll_ctrl) - mxs_reg_32(hw_ssp_status) - mxs_reg_32(hw_ssp_dll_sts) - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) + mxs_reg_32(hw_ssp_ctrl0); + mxs_reg_32(hw_ssp_cmd0); + mxs_reg_32(hw_ssp_cmd1); + mxs_reg_32(hw_ssp_xfer_size); + mxs_reg_32(hw_ssp_block_size); + mxs_reg_32(hw_ssp_compref); + mxs_reg_32(hw_ssp_compmask); + mxs_reg_32(hw_ssp_timing); + mxs_reg_32(hw_ssp_ctrl1); + mxs_reg_32(hw_ssp_data); + mxs_reg_32(hw_ssp_sdresp0); + mxs_reg_32(hw_ssp_sdresp1); + mxs_reg_32(hw_ssp_sdresp2); + mxs_reg_32(hw_ssp_sdresp3); + mxs_reg_32(hw_ssp_ddr_ctrl); + mxs_reg_32(hw_ssp_dll_ctrl); + mxs_reg_32(hw_ssp_status); + mxs_reg_32(hw_ssp_dll_sts); + mxs_reg_32(hw_ssp_debug); + mxs_reg_32(hw_ssp_version); }; #endif +static inline int mxs_ssp_bus_id_valid(int bus) +{ +#if defined(CONFIG_SOC_MX23) + const unsigned int mxs_ssp_chan_count = 2; +#elif defined(CONFIG_SOC_MX28) + const unsigned int mxs_ssp_chan_count = 4; +#endif + + if (bus >= mxs_ssp_chan_count) + return 0; + + if (bus < 0) + return 0; + + return 1; +} + +static inline int mxs_ssp_clock_by_bus(unsigned int clock) +{ +#if defined(CONFIG_SOC_MX23) + return 0; +#elif defined(CONFIG_SOC_MX28) + return clock; +#endif +} + +static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) +{ + switch (port) { + case 0: + return (struct mxs_ssp_regs *)MXS_SSP0_BASE; + case 1: + return (struct mxs_ssp_regs *)MXS_SSP1_BASE; +#ifdef CONFIG_SOC_MX28 + case 2: + return (struct mxs_ssp_regs *)MXS_SSP2_BASE; + case 3: + return (struct mxs_ssp_regs *)MXS_SSP3_BASE; +#endif + default: + return NULL; + } +} +#endif + #define SSP_CTRL0_SFTRST (1 << 31) #define SSP_CTRL0_CLKGATE (1 << 30) #define SSP_CTRL0_RUN (1 << 29) @@ -72,6 +124,11 @@ struct mxs_ssp_regs { #define SSP_CTRL0_GET_RESP (1 << 17) #define SSP_CTRL0_ENABLE (1 << 16) +#ifdef CONFIG_SOC_MX23 +#define SSP_CTRL0_XFER_COUNT_OFFSET 0 +#define SSP_CTRL0_XFER_COUNT_MASK 0xffff +#endif + #define SSP_CMD0_SOFT_TERMINATE (1 << 26) #define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) #define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) @@ -79,6 +136,12 @@ struct mxs_ssp_regs { #define SSP_CMD0_SLOW_CLKING_EN (1 << 22) #define SSP_CMD0_CONT_CLKING_EN (1 << 21) #define SSP_CMD0_APPEND_8CYC (1 << 20) +#if defined(CONFIG_SOC_MX23) +#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) +#define SSP_CMD0_BLOCK_SIZE_OFFSET 16 +#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) +#define SSP_CMD0_BLOCK_COUNT_OFFSET 8 +#endif #define SSP_CMD0_CMD_MASK 0xff #define SSP_CMD0_CMD_OFFSET 0 #define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 @@ -152,6 +215,7 @@ struct mxs_ssp_regs { #define SSP_CMD1_CMD_ARG_MASK 0xffffffff #define SSP_CMD1_CMD_ARG_OFFSET 0 +#if defined(CONFIG_SOC_MX28) #define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff #define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 @@ -159,6 +223,7 @@ struct mxs_ssp_regs { #define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 #define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf #define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 +#endif #define SSP_COMPREF_REFERENCE_MASK 0xffffffff #define SSP_COMPREF_REFERENCE_OFFSET 0