X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=arch%2Fmips%2Fcpu%2Fmips32%2Fcache.S;h=12f656cad0a7746f1cbcb2c56a3238f04c67c198;hb=8b485ba12b0defa0c4ed3559789250238f8331a8;hp=117fc56df7944ee2135a5acd7c94735f2cd73e36;hpb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;p=karo-tx-uboot.git

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 117fc56df7..12f656cad0 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -18,7 +18,7 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
-#define RA		t8
+#define RA		t9
 
 /*
  * 16kB is the maximum size of instruction and data caches on MIPS 4K,
@@ -128,8 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
 	move	RA, ra
 	li	t2, CONFIG_SYS_ICACHE_SIZE
 	li	t3, CONFIG_SYS_DCACHE_SIZE
-	li	t4, CONFIG_SYS_CACHELINE_SIZE
-	move	t5, t4
+	li	t8, CONFIG_SYS_CACHELINE_SIZE
 
 	li	v0, MIPS_MAX_CACHE_SIZE
 
@@ -156,17 +155,17 @@ NESTED(mips_cache_reset, 0, ra)
 	 * Initialize the I-cache first,
 	 */
 	move	a1, t2
-	move	a2, t4
-	PTR_LA	t7, mips_init_icache
-	jalr	t7
+	move	a2, t8
+	PTR_LA	v1, mips_init_icache
+	jalr	v1
 
 	/*
 	 * then initialize D-cache.
 	 */
 	move	a1, t3
-	move	a2, t5
-	PTR_LA	t7, mips_init_dcache
-	jalr	t7
+	move	a2, t8
+	PTR_LA	v1, mips_init_dcache
+	jalr	v1
 
 	jr	RA
 	END(mips_cache_reset)