X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=arch%2Fx86%2Fkernel%2Fapic%2Fapic.c;h=24e94ce454e2363e6ad14ae2e4cff6c4ac492ab4;hb=7b6e28c38f7cded35b8ca7e9d65bd01b45a0e8fa;hp=3ca3e46aa405ff606c205e849e9470735405f4cf;hpb=57e6bbcb4beb4c87aa93e78a1db08fdaab9ee65f;p=karo-tx-linux.git

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 3ca3e46aa405..24e94ce454e2 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -336,6 +336,13 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
 	apic_write(APIC_LVTT, lvtt_value);
 
 	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
+		/*
+		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
+		 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
+		 * According to Intel, MFENCE can do the serialization here.
+		 */
+		asm volatile("mfence" : : : "memory");
+
 		printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
 		return;
 	}