X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=board%2Fesd%2Fpmc440%2Fpmc440.c;h=ec9255243c472c18014a3f5b303695472e717689;hb=0bf7de838096e804f0cece8f2d94905477381b6e;hp=119cbf2627312721b8b9a4ef098f72dffe30fa3a;hpb=cae26e2fdd9934644086fda9f7cbc336a1fe5ce8;p=karo-tx-uboot.git

diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 119cbf2627..ec9255243c 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -148,29 +148,29 @@ int board_early_init_f(void)
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffff7ef);
-	mtdcr(uic0tr, 0x00000000);
-	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffc7f5);
-	mtdcr(uic1tr, 0x00000000);
-	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
-	mtdcr(uic2er, 0x00000000);	/* disable all */
-	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic2pr, 0x27ffffff);
-	mtdcr(uic2tr, 0x00000000);
-	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ef);
+	mtdcr(UIC0TR, 0x00000000);
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffc7f5);
+	mtdcr(UIC1TR, 0x00000000);
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0x27ffffff);
+	mtdcr(UIC2TR, 0x00000000);
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
 	/* select Ethernet pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
@@ -208,7 +208,7 @@ int misc_init_f(void)
 
 	if (getenv("pciearly") && (!is_monarch())) {
 		printf("PCI:   early target init\n");
-		pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+		pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
 		pci_target_init(&hose);
 	}
 	return 0;
@@ -568,42 +568,42 @@ void pci_target_init(struct pci_controller *hose)
 	 * Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
 						/* and enable region */
 
 	if (!is_monarch()) {
 		ptmla_str = getenv("ptm1la");
 		ptmms_str = getenv("ptm1ms");
 		if(NULL != ptmla_str && NULL != ptmms_str ) {
-			out32r(PCIX0_PTM1MS,
+			out32r(PCIL0_PTM1MS,
 			       simple_strtoul(ptmms_str, NULL, 16));
-			out32r(PCIX0_PTM1LA,
+			out32r(PCIL0_PTM1LA,
 			       simple_strtoul(ptmla_str, NULL, 16));
 		} else {
 			/* BAR1: default top 64MB of RAM */
-			out32r(PCIX0_PTM1MS, 0xfc000001);
-			out32r(PCIX0_PTM1LA, 0x0c000000);
+			out32r(PCIL0_PTM1MS, 0xfc000001);
+			out32r(PCIL0_PTM1LA, 0x0c000000);
 		}
 	} else {
 		/* BAR1: default: complete 256MB RAM */
-		out32r(PCIX0_PTM1MS, 0xf0000001);
-		out32r(PCIX0_PTM1LA, 0x00000000);
+		out32r(PCIL0_PTM1MS, 0xf0000001);
+		out32r(PCIL0_PTM1LA, 0x00000000);
 	}
 
 	ptmla_str = getenv("ptm2la");		/* Local Addr. Reg */
 	ptmms_str = getenv("ptm2ms");		/* Memory Size/Attribute */
 	if(NULL != ptmla_str && NULL != ptmms_str ) {
-		out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
-		out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+		out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+		out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
 	} else {
 		/* BAR2: default: 4MB FPGA */
-		out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
-		out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+		out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+		out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
 	}
 
 	if (is_monarch()) {