X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=board%2Fttcontrol%2Fvision2%2Fvision2.c;h=b4d3994158da0d6417e211273ad62ce3cea1c5b9;hb=8b485ba12b0defa0c4ed3559789250238f8331a8;hp=565c4d05ba765b4775b4b36551e752b64229e231;hpb=9023ae305919d0aecb4a22726b9d08c6b08189d7;p=karo-tx-uboot.git diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index 565c4d05ba..b4d3994158 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -4,48 +4,30 @@ * * (C) Copyright 2009 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include -#include #include -#include -#include +#include +#include +#include #include -#include #include #include +#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - -static u32 system_rev; +#include -extern int mx51_fb_init(struct fb_videomode *mode); +DECLARE_GLOBAL_DATA_PTR; -static struct fb_videomode nec_nl6448bc26_09c = { +static struct fb_videomode const nec_nl6448bc26_09c = { "NEC_NL6448BC26-09C", 60, /* Refresh */ 640, /* xres */ @@ -69,92 +51,67 @@ void hw_watchdog_reset(void) int val; /* toggle watchdog trigger pin */ - val = mxc_gpio_get(66); + val = gpio_get_value(IMX_GPIO_NR(3, 2)); val = val ? 0 : 1; - mxc_gpio_set(66, val); + gpio_set_value(IMX_GPIO_NR(3, 2), val); } #endif static void init_drive_strength(void) { - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); - - /* Setting pad options */ - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} - -u32 get_board_rev(void) -{ - system_rev = get_cpu_rev(); - - return system_rev; + static const iomux_v3_cfg_t ddr_pads[] = { + NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0), + NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE), + NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0), + NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH), + NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS, + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS, + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE), + NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0), + NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP), + NEW_PAD_CTRL(MX51_GRP_INMODE1, 0), + NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED), + NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED), + NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED), + NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED), + + NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3, + MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); } int dram_init(void) @@ -178,142 +135,102 @@ static void setup_weim(void) static void setup_uart(void) { - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST; - /* console RX on Pin EIM_D25 */ - mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad); - /* console TX on Pin EIM_D26 */ - mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad); + static const iomux_v3_cfg_t uart_pads[] = { + MX51_PAD_EIM_D25__UART3_RXD, /* console RX */ + MX51_PAD_EIM_D26__UART3_TXD, /* console TX */ + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } #ifdef CONFIG_MXC_SPI void spi_io_init(void) { - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* - * SS1 will be used as GPIO because of uninterrupted - * long SPI transmissions (GPIO4_25) - */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7); - mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + static const iomux_v3_cfg_t spi_pads[] = { + NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS | + PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS | + PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS | + PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST), + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); } static void reset_peripherals(int reset) { +#ifdef CONFIG_VISION2_HW_1_0 + static const iomux_v3_cfg_t fec_cfg_pads[] = { + /* RXD1 */ + NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL), + /* RXD2 */ + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL), + /* RXD3 */ + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL), + /* RXER */ + NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL), + /* COL */ + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL), + /* RCLK */ + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL), + /* RXD0 */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL), + }; + + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), + MX51_PAD_NANDF_D9__FEC_RDATA0, + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), + MX51_PAD_EIM_CS4__FEC_RX_ER, + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), + }; +#endif + if (reset) { /* reset_n is on NANDF_D15 */ - mxc_gpio_set(89, 0); - mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IMX_GPIO_NR(3, 25), 0); #ifdef CONFIG_VISION2_HW_1_0 /* * set FEC Configuration lines * set levels of FEC config lines */ - mxc_gpio_set(75, 0); - mxc_gpio_set(74, 1); - mxc_gpio_set(95, 1); - mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IMX_GPIO_NR(3, 11), 0); + gpio_direction_output(IMX_GPIO_NR(3, 10), 1); + gpio_direction_output(IMX_GPIO_NR(3, 31), 1); /* set direction of FEC config lines */ - mxc_gpio_set(59, 0); - mxc_gpio_set(60, 0); - mxc_gpio_set(61, 0); - mxc_gpio_set(55, 1); - mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT); - - /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */ - mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); - /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1); - /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1); - /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1); - /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */ - mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3); - /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */ - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3); - /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */ - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3); + gpio_direction_output(IMX_GPIO_NR(2, 27), 0); + gpio_direction_output(IMX_GPIO_NR(2, 28), 0); + gpio_direction_output(IMX_GPIO_NR(2, 29), 0); + gpio_direction_output(IMX_GPIO_NR(2, 23), 1); + + imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, + ARRAY_SIZE(fec_cfg_pads)); #endif - /* - * activate reset_n pin - * Select mux mode: ALT3 mux port: NAND D15 - */ - mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D15, - PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX); + /* activate reset_n pin */ + imx_iomux_v3_setup_pad( + NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25, + PAD_CTL_DSE_MAX)); } else { /* set FEC Control lines */ - mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(IMX_GPIO_NR(3, 25)); udelay(500); #ifdef CONFIG_VISION2_HW_1_0 - /* FEC RDATA[3] */ - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); - - /* FEC RDATA[2] */ - mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); - - /* FEC RDATA[1] */ - mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); - - /* FEC RDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); - - /* FEC RX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); - - /* FEC RX_ER */ - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); - - /* FEC COL */ - mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); + imx_iomux_v3_setup_multiple_pads(fec_pads, + ARRAY_SIZE(fec_pads)); #endif } } @@ -321,59 +238,69 @@ static void reset_peripherals(int reset) static void power_init_mx51(void) { unsigned int val; + struct pmic *p; + int ret; + + ret = pmic_init(I2C_PMIC); + if (ret) + return; + + p = pmic_get("FSL_PMIC"); + if (!p) + return; /* Write needed to Power Gate 2 register */ - val = pmic_reg_read(REG_POWER_MISC); + pmic_reg_read(p, REG_POWER_MISC, &val); /* enable VCAM with 2.775V to enable read from PMIC */ val = VCAMCONFIG | VCAMEN; - pmic_reg_write(REG_MODE_1, val); + pmic_reg_write(p, REG_MODE_1, val); /* * Set switchers in Auto in NORMAL mode & STANDBY mode * Setup the switcher mode for SW1 & SW2 */ - val = pmic_reg_read(REG_SW_4); + pmic_reg_read(p, REG_SW_4, &val); val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | (SWMODE_MASK << SWMODE2_SHIFT))); val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(REG_SW_4, val); + pmic_reg_write(p, REG_SW_4, val); /* Setup the switcher mode for SW3 & SW4 */ - val = pmic_reg_read(REG_SW_5); + pmic_reg_read(p, REG_SW_5, &val); val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | (SWMODE_MASK << SWMODE3_SHIFT)); val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); - pmic_reg_write(REG_SW_5, val); + pmic_reg_write(p, REG_SW_5, val); /* Set VGEN3 to 1.8V, VCAM to 3.0V */ - val = pmic_reg_read(REG_SETTING_0); + pmic_reg_read(p, REG_SETTING_0, &val); val &= ~(VCAM_MASK | VGEN3_MASK); val |= VCAM_3_0; - pmic_reg_write(REG_SETTING_0, val); + pmic_reg_write(p, REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */ - val = pmic_reg_read(REG_SETTING_1); + pmic_reg_read(p, REG_SETTING_1, &val); val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8; - pmic_reg_write(REG_SETTING_1, val); + pmic_reg_write(p, REG_SETTING_1, val); /* Configure VGEN3 and VCAM regulators to use external PNP */ val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(REG_MODE_1, val); + pmic_reg_write(p, REG_MODE_1, val); udelay(200); /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(REG_MODE_1, val); + pmic_reg_write(p, REG_MODE_1, val); - val = pmic_reg_read(REG_POWER_CTL2); + pmic_reg_read(p, REG_POWER_CTL2, &val); val |= WDIRESET; - pmic_reg_write(REG_POWER_CTL2, val); + pmic_reg_write(p, REG_POWER_CTL2, val); udelay(2500); @@ -382,168 +309,98 @@ static void power_init_mx51(void) static void setup_gpios(void) { - unsigned int i; - - /* CAM_SUP_DISn, GPIO1_7 */ - mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82); + static const iomux_v3_cfg_t gpio_pads_1[] = { + NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* CAM_SUP_DISn */ + NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* DAB Display EN */ + NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* WDOG_TRIGGER */ + }; + + static const iomux_v3_cfg_t gpio_pads_2[] = { + NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* Display2 TxEN */ + NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* DAB Light EN */ + NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* AUDIO_MUTE */ + NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* SPARE_OUT */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* BEEPER_EN */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* POWER_OFF */ + NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* FRAM_WE */ + NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE | + PAD_CTL_DSE_MED), /* EXPANSION_EN */ + MX51_PAD_GPIO1_2__PWM1_PWMO, + }; - /* DAB Display EN, GPIO3_1 */ - mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82); + unsigned int i; - /* WDOG_TRIGGER, GPIO3_2 */ - mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82); + imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1)); /* Now we need to trigger the watchdog */ WATCHDOG_RESET(); - /* Display2 TxEN, GPIO3_3 */ - mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82); - - /* DAB Light EN, GPIO3_4 */ - mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82); - - /* AUDIO_MUTE, GPIO3_5 */ - mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82); - - /* SPARE_OUT, GPIO3_6 */ - mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4); - mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82); - - /* BEEPER_EN, GPIO3_26 */ - mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82); - - /* POWER_OFF, GPIO3_27 */ - mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82); - - /* FRAM_WE, GPIO3_30 */ - mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82); - - /* EXPANSION_EN, GPIO4_26 */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82); - - /* PWM Output GPIO1_2 */ - mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1); + imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2)); /* * Set GPIO1_4 to high and output; it is used to reset * the system on reboot */ - mxc_gpio_set(4, 1); - mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT); - - mxc_gpio_set(7, 0); - mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT); - for (i = 65; i < 71; i++) { - mxc_gpio_set(i, 0); - mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT); - } + gpio_direction_output(IMX_GPIO_NR(1, 4), 1); + + gpio_direction_output(IMX_GPIO_NR(1, 7), 0); + for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++) + gpio_direction_output(i, 0); - mxc_gpio_set(94, 0); - mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IMX_GPIO_NR(3, 30), 0); /* Set POWER_OFF high */ - mxc_gpio_set(91, 1); - mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IMX_GPIO_NR(3, 27), 1); - mxc_gpio_set(90, 0); - mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IMX_GPIO_NR(3, 26), 0); - mxc_gpio_set(122, 0); - mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IMX_GPIO_NR(4, 26), 0); - mxc_gpio_set(121, 1); - mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IMX_GPIO_NR(4, 25), 1); WATCHDOG_RESET(); } static void setup_fec(void) { - /*FEC_MDIO*/ - mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD); - - /*FEC_MDC*/ - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); - - /* FEC RDATA[3] */ - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); - - /* FEC RDATA[2] */ - mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); - - /* FEC RDATA[1] */ - mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); - - /* FEC RDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); - - /* FEC TDATA[3] */ - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); - - /* FEC TDATA[2] */ - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); - - /* FEC TDATA[1] */ - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); - - /* FEC TDATA[0] */ - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); - - /* FEC TX_EN */ - mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); - - /* FEC TX_ER */ - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); - - /* FEC TX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); - - /* FEC TX_COL */ - mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); - - /* FEC RX_CLK */ - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); - - /* FEC RX_CRS */ - mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); - - /* FEC RX_ER */ - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); - - /* FEC RX_DV */ - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + MX51_PAD_NANDF_CS3__FEC_MDC, + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), + MX51_PAD_NANDF_D9__FEC_RDATA0, + MX51_PAD_NANDF_CS6__FEC_TDATA3, + MX51_PAD_NANDF_CS5__FEC_TDATA2, + MX51_PAD_NANDF_CS4__FEC_TDATA1, + MX51_PAD_NANDF_D8__FEC_TDATA0, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_EIM_CS4__FEC_RX_ER, + NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } struct fsl_esdhc_cfg esdhc_cfg[1] = { - {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC1_BASE_ADDR}, }; int get_mmc_getcd(u8 *cd, struct mmc *mmc) @@ -551,7 +408,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(0); + *cd = gpio_get_value(IMX_GPIO_NR(1, 0)); else *cd = 0; @@ -561,61 +418,50 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc) #ifdef CONFIG_FSL_ESDHC int board_mmc_init(bd_t *bis) { - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA2, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX51_PIN_SD1_DATA3, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | - PAD_CTL_PUE_PULL | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_0, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_0, - PAD_CTL_HYS_ENABLE); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_HYS_ENABLE); - + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), + NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), + }; + + imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } #endif +void lcd_enable(void) +{ + static const iomux_v3_cfg_t lcd_pads[] = { + MX51_PAD_DI1_PIN2__DI1_PIN2, + MX51_PAD_DI1_PIN3__DI1_PIN3, + }; + + int ret; + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + gpio_set_value(IMX_GPIO_NR(1, 2), 1); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2, + NO_PAD_CTRL)); + + ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666); + if (ret) + puts("LCD cannot be configured\n"); +} + int board_early_init_f(void) { @@ -623,10 +469,9 @@ int board_early_init_f(void) init_drive_strength(); /* Setup debug led */ - mxc_gpio_set(6, 0); - mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT); - mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + gpio_direction_output(IMX_GPIO_NR(1, 6), 0); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST)); /* wait a little while to give the pll time to settle */ sdelay(100000); @@ -644,36 +489,24 @@ int board_early_init_f(void) static void backlight(int on) { if (on) { - mxc_gpio_set(65, 1); + gpio_set_value(IMX_GPIO_NR(3, 1), 1); udelay(10000); - mxc_gpio_set(68, 1); + gpio_set_value(IMX_GPIO_NR(3, 4), 1); } else { - mxc_gpio_set(65, 0); - mxc_gpio_set(68, 0); + gpio_set_value(IMX_GPIO_NR(3, 1), 0); + gpio_set_value(IMX_GPIO_NR(3, 4), 0); } } -void lcd_enable(void) -{ - int ret; - - mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0); - - mxc_gpio_set(2, 1); - mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0); - - ret = mx51_fb_init(&nec_nl6448bc26_09c); - if (ret) - puts("LCD cannot be configured\n"); -} - int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */ /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + lcd_enable(); + + backlight(1); + return 0; } @@ -697,6 +530,15 @@ int board_late_init(void) return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int checkboard(void) { puts("Board: TTControl Vision II CPU V\n");