X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=drivers%2Fnet%2F4xx_enet.c;h=2fac64167b9fd418f9a649f137ae0c11cfcc55b1;hb=0bf7de838096e804f0cece8f2d94905477381b6e;hp=19782695998d4bea6036212dd26084d7cf4b92b2;hpb=cb5473205206c7f14cbb1e747f28ec75b48826e2;p=karo-tx-uboot.git diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 1978269599..2fac64167b 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -1,4 +1,6 @@ /*-----------------------------------------------------------------------------+ + * This source code is dual-licensed. You may use it under the terms of the + * GNU General Public License version 2, or under the license below. * * This source code has been made available to you by IBM on an AS-IS * basis. Anyone receiving this source is licensed under IBM @@ -42,7 +44,7 @@ * RX descriptor address up to the next cache line boundary. * 16-Jan-00 Added support for booting with IP of 0x0 MKW * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the - * EMAC_RXM register. JWB + * EMAC0_RXM register. JWB * 12-Mar-01 anne-sophie.harnois@nextream.fr * - Variables are compatible with those already defined in * include/net.h @@ -56,7 +58,7 @@ * 08-May-01 stefan.roese@esd-electronics.com * - MAL error handling added (eth_init called again) * 13-Nov-01 stefan.roese@esd-electronics.com - * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex + * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex * 04-Jan-02 stefan.roese@esd-electronics.com * - Wait for PHY auto negotiation to complete added * 06-Feb-02 stefan.roese@esd-electronics.com @@ -259,9 +261,6 @@ static const struct fixed_phy_port fixed_phy_port[] = { /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. *-----------------------------------------------------------------------------*/ -#if !defined(CONFIG_NET_MULTI) -struct eth_device *emac0_dev = NULL; -#endif /* * Get count of EMAC devices (doesn't have to be the max. possible number @@ -320,9 +319,9 @@ static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) defined(CONFIG_405EX) u32 val; - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); + mtsdr(SDR0_MFR, val); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) u32 val; @@ -339,9 +338,9 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) defined(CONFIG_405EX) u32 val; - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); + mtsdr(SDR0_MFR, val); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) u32 val; @@ -360,19 +359,19 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) EMAC_4XX_HW_PST hw_p = dev->priv; u32 val = 10000; - out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2))); #else - mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum)); #endif - mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); + mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum)); /* wait for reset */ - while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { + while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) { udelay (1000); /* Delay 1 MS so as not to hammer the register */ val--; if (val == 0) @@ -383,7 +382,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) emac_loopback_enable(hw_p); /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); /* remove clocks for EMAC internal loopback */ emac_loopback_disable(hw_p); @@ -409,7 +408,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) unsigned long zmiifer; unsigned long rmiifer; - mfsdr(sdr_pfc1, pfc1); + mfsdr(SDR0_PFC1, pfc1); pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); zmiifer = 0; @@ -486,7 +485,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* Ensure we setup mdio for this devnum and ONLY this devnum */ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)ZMII0_FER, zmiifer); out_be32((void *)RGMII_FER, rmiifer); return ((int)pfc1); @@ -499,27 +498,27 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) unsigned long zmiifer=0x0; unsigned long pfc1; - mfsdr(sdr_pfc1, pfc1); + mfsdr(SDR0_PFC1, pfc1); pfc1 &= SDR0_PFC1_SELECT_MASK; switch (pfc1) { case SDR0_PFC1_SELECT_CONFIG_2: /* 1 x GMII port */ - out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)ZMII0_FER, 0x00); out_be32((void *)RGMII_FER, 0x00000037); bis->bi_phymode[0] = BI_PHYMODE_GMII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; case SDR0_PFC1_SELECT_CONFIG_4: /* 2 x RGMII ports */ - out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)ZMII0_FER, 0x00); out_be32((void *)RGMII_FER, 0x00000055); bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII; break; case SDR0_PFC1_SELECT_CONFIG_6: /* 2 x SMII ports */ - out_be32((void *)ZMII_FER, + out_be32((void *)ZMII0_FER, ((ZMII_FER_SMII) << ZMII_FER_V(0)) | ((ZMII_FER_SMII) << ZMII_FER_V(1))); out_be32((void *)RGMII_FER, 0x00000000); @@ -528,7 +527,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) break; case SDR0_PFC1_SELECT_CONFIG_1_2: /* only 1 x MII supported */ - out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); + out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); out_be32((void *)RGMII_FER, 0x00000000); bis->bi_phymode[0] = BI_PHYMODE_MII; bis->bi_phymode[1] = BI_PHYMODE_NONE; @@ -538,9 +537,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } /* Ensure we setup mdio for this devnum and ONLY this devnum */ - zmiifer = in_be32((void *)ZMII_FER); + zmiifer = in_be32((void *)ZMII0_FER); zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)ZMII0_FER, zmiifer); return ((int)0x0); } @@ -871,8 +870,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) + u32 opbfreq; sys_info_t sysinfo; -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ +#if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) @@ -953,18 +953,18 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* NOTE: Therefore, disable all other EMACS, since we handle */ /* NOTE: only one emac at a time */ reg = 0; - out_be32((void *)ZMII_FER, 0); + out_be32((void *)ZMII0_FER, 0); udelay (100); #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); #elif defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); #endif - out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); + out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum)); #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ #if defined(CONFIG_405EX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); @@ -976,13 +976,13 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) emac_loopback_enable(hw_p); /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); /* remove clocks for EMAC internal loopback */ emac_loopback_disable(hw_p); failsafe = 1000; - while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { + while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) { udelay (1000); failsafe--; } @@ -997,17 +997,18 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; - if (sysinfo.freqOPB <= 50000000); - else if (sysinfo.freqOPB <= 66666667) - mode_reg |= EMAC_M1_OBCI_66; - else if (sysinfo.freqOPB <= 83333333) - mode_reg |= EMAC_M1_OBCI_83; - else if (sysinfo.freqOPB <= 100000000) - mode_reg |= EMAC_M1_OBCI_100; + opbfreq = sysinfo.freqOPB / 1000000; + if (opbfreq <= 50); + else if (opbfreq <= 66) + mode_reg |= EMAC_MR1_OBCI_66; + else if (opbfreq <= 83) + mode_reg |= EMAC_MR1_OBCI_83; + else if (opbfreq <= 100) + mode_reg |= EMAC_MR1_OBCI_100; else - mode_reg |= EMAC_M1_OBCI_GT100; + mode_reg |= EMAC_MR1_OBCI_GT100; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ @@ -1040,9 +1041,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif } - mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg); - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); + mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); /* Configure GPCS interface to recommended setting for SGMII */ miiphy_reset(dev->name, reg); @@ -1120,7 +1121,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) @@ -1240,21 +1240,21 @@ get_speed: !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ !defined(CONFIG_460EX) && !defined(CONFIG_460GT) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) - mfsdr(sdr_mfr, reg); + mfsdr(SDR0_MFR, reg); if (speed == 100) { reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; } else { reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; } - mtsdr(sdr_mfr, reg); + mtsdr(SDR0_MFR, reg); #endif /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in_be32((void *)ZMII_SSR); + reg = in_be32((void *)ZMII0_SSR); if ( (speed == 100) || (speed == 1000) ) - out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum))); else - out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum)))); if ((devnum == 2) || (devnum == 3)) { if (speed == 1000) @@ -1302,13 +1302,13 @@ get_speed: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); /* Errata 1.12: MAL_1 -- Disable MAL bursting */ if (get_pvr() == PVR_440GP_RB) { - mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); } #endif @@ -1381,7 +1381,7 @@ get_speed: reg = reg << 8; reg |= dev->enetaddr[1]; - out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); + out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg); reg = 0x00000000; reg |= dev->enetaddr[2]; /* set low address */ @@ -1392,97 +1392,97 @@ get_speed: reg = reg << 8; reg |= dev->enetaddr[5]; - out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); + out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg); switch (devnum) { case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); #else - mtdcr (maltxctp1r, hw_p->tx_phys); + mtdcr (MAL0_TXCTP1R, hw_p->tx_phys); #endif #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) - mtdcr (malrxctp8r, hw_p->rx_phys); + mtdcr (MAL0_RXCTP8R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16); #else - mtdcr (malrxctp1r, hw_p->rx_phys); + mtdcr (MAL0_RXCTP1R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16); #endif break; #if defined (CONFIG_440GX) case 2: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp2r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP2R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); - mtdcr (malrxbattr, 0x0); - mtdcr (malrxctp3r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_RXCTP3R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_440GX */ #if defined (CONFIG_460GT) case 2: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp16r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP16R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); - mtdcr (malrxctp24r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP24R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_460GT */ case 0: default: /* setup MAL tx & rx channel pointers */ #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (maltxctp0r, hw_p->tx_phys); - mtdcr (malrxctp0r, hw_p->rx_phys); + mtdcr (MAL0_TXCTP0R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP0R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16); break; } /* Enable MAL transmit and receive channels */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2))); #else - mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); #endif - mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); + mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE); - mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); /* set rx-/tx-fifo size */ mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; @@ -1493,51 +1493,51 @@ get_speed: defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); + mfsdr (SDR0_PFC1, pfc1); pfc1 |= SDR0_PFC1_EM_1000; - mtsdr (sdr_pfc1, pfc1); + mtsdr (SDR0_PFC1, pfc1); #endif - mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; + mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST; } else if (speed == _100BASET) - mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; + mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST; else mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ if (duplex == FULL) - mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; + mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); /* Enable broadcast and indvidual address */ /* TBS: enabling runts as some misbehaved nics will send runts */ - out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); /* we probably need to set the tx mode1 reg? maybe at tx time */ /* set transmit request threshold register */ - out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif /* defined(CONFIG_440) */ - out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); + out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003); /* Frame gap set */ - out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); /* Set EMAC IER */ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; if (speed == _100BASET) hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; - out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ - out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier); if (hw_p->first_init == 0) { /* @@ -1596,8 +1596,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, sync(); - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, - in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, + in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0); #ifdef INFO_4XX_ENET hw_p->stats.pkts_tx++; #endif @@ -1607,9 +1607,9 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, *-----------------------------------------------------------------------*/ time_start = get_timer (0); while (1) { - temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); + temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr); /* loop until either TINT turns on or 3 seconds elapse */ - if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { + if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) { /* transmit is done, so now check for errors * If there is an error, an interrupt should * happen when we return @@ -1641,11 +1641,7 @@ int enetInt (struct eth_device *dev) * Because the mal is generic, we need to get the current * eth device */ -#if defined(CONFIG_NET_MULTI) dev = eth_get_dev(); -#else - dev = emac0_dev; -#endif hw_p = dev->priv; @@ -1669,7 +1665,7 @@ int enetInt (struct eth_device *dev) /* look at MAL and EMAC error interrupts */ if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { /* we have a MAL error interrupt */ - mal_isr = mfdcr(malesr); + mal_isr = mfdcr(MAL0_ESR); mal_err(dev, mal_isr, uic_mal_err, MAL_UIC_DEF, MAL_UIC_ERR); @@ -1682,7 +1678,7 @@ int enetInt (struct eth_device *dev) /* look for EMAC errors */ if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr); emac_err(dev, emac_isr); /* clear EMAC error interrupt status bits */ @@ -1695,8 +1691,8 @@ int enetInt (struct eth_device *dev) /* handle MAX TX EOB interrupt from a tx */ if (uic_mal & UIC_MAL_TXEOB) { /* clear MAL interrupt status bits */ - mal_eob = mfdcr(maltxeobisr); - mtdcr(maltxeobisr, mal_eob); + mal_eob = mfdcr(MAL0_TXEOBISR); + mtdcr(MAL0_TXEOBISR, mal_eob); mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); /* indicate that we serviced an interrupt */ @@ -1707,7 +1703,7 @@ int enetInt (struct eth_device *dev) /* handle MAL RX EOB interupt from a receive */ /* check for EOB on valid channels */ if (uic_mal & UIC_MAL_RXEOB) { - mal_eob = mfdcr(malrxeobisr); + mal_eob = mfdcr(MAL0_RXEOBISR); if (mal_eob & (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { /* push packet to upper layer */ @@ -1721,6 +1717,15 @@ int enetInt (struct eth_device *dev) rc = 0; } } +#if defined(CONFIG_405EZ) + /* + * On 405EZ the RX-/TX-interrupts are coalesced into + * one IRQ bit in the UIC. We need to acknowledge the + * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. + */ + mtsdr(SDR0_ICINTSTAT, + SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); +#endif /* defined(CONFIG_405EZ) */ } while (serviced); return (rc); @@ -1735,11 +1740,11 @@ static void mal_err (struct eth_device *dev, unsigned long isr, { EMAC_4XX_HW_PST hw_p = dev->priv; - mtdcr (malesr, isr); /* clear interrupt */ + mtdcr (MAL0_ESR, isr); /* clear interrupt */ /* clear DE interrupt */ - mtdcr (maltxdeir, 0xC0000000); - mtdcr (malrxdeir, 0x80000000); + mtdcr (MAL0_TXDEIR, 0xC0000000); + mtdcr (MAL0_RXDEIR, 0x80000000); #ifdef INFO_4XX_ENET printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); @@ -1756,7 +1761,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr) EMAC_4XX_HW_PST hw_p = dev->priv; printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); - out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr); } /*-----------------------------------------------------------------------------+ @@ -1773,10 +1778,10 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) int i; int loop_count = 0; - rx_eob_isr = mfdcr (malrxeobisr); + rx_eob_isr = mfdcr (MAL0_RXEOBISR); if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { /* clear EOB */ - mtdcr (malrxeobisr, rx_eob_isr); + mtdcr (MAL0_RXEOBISR, rx_eob_isr); /* EMAC RX done */ while (1) { /* do all */ @@ -1916,10 +1921,10 @@ int ppc_4xx_eth_initialize (bd_t * bis) #if defined(CONFIG_440GX) unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); + mfsdr (SDR0_PFC1, pfc1); pfc1 &= ~(0x01e00000); pfc1 |= 0x01200000; - mtsdr (sdr_pfc1, pfc1); + mtsdr (SDR0_PFC1, pfc1); #endif /* first clear all mac-addresses */ @@ -1927,24 +1932,22 @@ int ppc_4xx_eth_initialize (bd_t * bis) memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { + int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START; switch (eth_num) { default: /* fall through */ case 0: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enetaddr, 6); + eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]); hw_addr[eth_num] = 0x0; break; #ifdef CONFIG_HAS_ETH1 case 1: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enet1addr, 6); + eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]); hw_addr[eth_num] = 0x100; break; #endif #ifdef CONFIG_HAS_ETH2 case 2: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enet2addr, 6); + eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]); #if defined(CONFIG_460GT) hw_addr[eth_num] = 0x300; #else @@ -1954,8 +1957,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) #endif #ifdef CONFIG_HAS_ETH3 case 3: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enet3addr, 6); + eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]); #if defined(CONFIG_460GT) hw_addr[eth_num] = 0x400; #else @@ -2043,10 +2045,10 @@ int ppc_4xx_eth_initialize (bd_t * bis) MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE | MAL_IER_PLBE; #endif - mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ - mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malier, mal_ier); + mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_IER, mal_ier); /* install MAL interrupt handler */ irq_install_handler (VECNUM_MAL_SERR, @@ -2067,60 +2069,13 @@ int ppc_4xx_eth_initialize (bd_t * bis) virgin = 1; } -#if defined(CONFIG_NET_MULTI) eth_register (dev); -#else - emac0_dev = dev; -#endif -#if defined(CONFIG_NET_MULTI) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register (dev->name, emac4xx_miiphy_read, emac4xx_miiphy_write); -#endif #endif } /* end for each supported device */ return 0; } - -#if !defined(CONFIG_NET_MULTI) -void eth_halt (void) { - if (emac0_dev) { - ppc_4xx_eth_halt(emac0_dev); - free(emac0_dev); - emac0_dev = NULL; - } -} - -int eth_init (bd_t *bis) -{ - ppc_4xx_eth_initialize(bis); - if (emac0_dev) { - return ppc_4xx_eth_init(emac0_dev, bis); - } else { - printf("ERROR: ethaddr not set!\n"); - return -1; - } -} - -int eth_send(volatile void *packet, int length) -{ - return (ppc_4xx_eth_send(emac0_dev, packet, length)); -} - -int eth_rx(void) -{ - return (ppc_4xx_eth_rx(emac0_dev)); -} - -int emac4xx_miiphy_initialize (bd_t * bis) -{ -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register ("ppc_4xx_eth0", - emac4xx_miiphy_read, emac4xx_miiphy_write); -#endif - - return 0; -} -#endif /* !defined(CONFIG_NET_MULTI) */