X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2FNETVIA.h;h=0fd635dc270fd86f4637fa2ea6dd72a7157c22af;hb=890880583d84607e36b52a785a96b167728bbf73;hp=e30be0987aa47619863424afe90229304ad54c25;hpb=f6e5739a68131998a5ae8aa0cf56a0316f810200;p=karo-tx-uboot.git diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index e30be0987a..0fd635dc27 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -1,24 +1,8 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -37,6 +21,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_NETVIA 1 /* ...on a NetVia board */ +#define CONFIG_SYS_TEXT_BASE 0x40000000 + #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 @@ -59,17 +45,17 @@ #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -81,51 +67,59 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_NISDOMAIN + #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND) -#else -#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE +/* #define CONFIG_CMD_NAND */ /* disabled */ #endif + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* * Low Level Configuration Settings @@ -135,65 +129,62 @@ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFF000000 +#define CONFIG_SYS_IMMR 0xFF000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0x40000000 #if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 0x4000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) +#define CONFIG_ENV_SIZE 0x4000 -#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_OFFSET_REDUND 0 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -203,10 +194,10 @@ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /*----------------------------------------------------------------------- @@ -215,9 +206,9 @@ * PCMCIA config., multi-function pin tri-state */ #ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) #else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) #endif /* CONFIG_CAN_DRIVER */ /*----------------------------------------------------------------------- @@ -225,20 +216,20 @@ *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register 11-27 *----------------------------------------------------------------------- */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) +#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 @@ -258,16 +249,16 @@ #if CONFIG_8xx_GCLK_FREQ == 50000000 -#define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#define CFG_SCCR (SCCR_TBS | \ +#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) +#define CONFIG_SYS_SCCR (SCCR_TBS | \ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) #elif CONFIG_8xx_GCLK_FREQ == 80000000 -#define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#define CFG_SCCR (SCCR_TBS | \ +#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) +#define CONFIG_SYS_SCCR (SCCR_TBS | \ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00 | SCCR_EBDF01) @@ -279,8 +270,8 @@ *----------------------------------------------------------------------- * */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 +/*#define CONFIG_SYS_DER 0x2002000F*/ +#define CONFIG_SYS_DER 0 /* * Init Memory Controller: @@ -294,15 +285,15 @@ * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ +#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) /* * BR3 and OR3 (SDRAM) @@ -312,43 +303,33 @@ #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) +#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) -#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) +#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) +#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) /* * Memory Periodic Timer Prescaler */ /* periodic timer for refresh */ -#define CFG_MAMR_PTA 208 +#define CONFIG_SYS_MAMR_PTA 208 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ /* * MAMR settings for SDRAM */ /* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - /* Ethernet at SCC2 */ #define CONFIG_SCC2_ENET -#define CONFIG_ARTOS /* include ARTOS support */ - /****************************************************************/ #define DSP_SIZE 0x00010000 /* 64K */ @@ -373,11 +354,11 @@ #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 #define STATUS_LED_BIT 0x00000001 /* bit 31 */ -#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) #define STATUS_LED_STATE STATUS_LED_BLINKING #define STATUS_LED_BIT1 0x00000002 /* bit 30 */ -#define STATUS_LED_PERIOD1 (CFG_HZ / 2) +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) #define STATUS_LED_STATE1 STATUS_LED_OFF #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ @@ -385,81 +366,6 @@ #endif -/*****************************************************************************/ - -#define CFG_NAND_LEGACY - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -/* NAND */ -#define CFG_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 - -#define CFG_MAX_NAND_DEVICE 1 - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0040; \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0100; \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0080; \ - } while(0) - -#define NAND_WAIT_READY(nand) \ - do { \ - while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \ - ; \ - } while (0) - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -#endif /*****************************************************************************/ @@ -511,16 +417,16 @@ static inline void __led_set(led_id_t mask, int state) } /* MAX3100 console */ -#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) #define MAX3100_SPI_RXD_BIT 0x00000008 -#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) #define MAX3100_SPI_TXD_BIT 0x00000004 -#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) #define MAX3100_SPI_CLK_BIT 0x00000002 -#define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) +#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) #define MAX3100_CS_BIT 0x0010 #endif