X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Flubbock.h;h=5886a155dcbe3e66590e169ee0513b84feb3c5ce;hb=c68436fa427a69ea308d74c410067507d6c7103b;hp=4adf2542219fbaeb7d4284ef41f28a087c74b0a2;hpb=85fad497b3c2e99fa48d18351d2898cf8cdbe898;p=karo-tx-uboot.git diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 4adf254221..5886a155dc 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -34,33 +34,37 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ #define CONFIG_LCD 1 #ifdef CONFIG_LCD #define CONFIG_SHARP_LM8V31 #endif -#define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 +#define CONFIG_MMC +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_TEXT_BASE 0x0 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * Hardware drivers */ -#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96 #define CONFIG_LAN91C96_BASE 0x0C000000 /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ +#define CONFIG_CONS_INDEX 3 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -82,7 +86,6 @@ */ #include -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT @@ -104,45 +107,33 @@ /* * Miscellaneous configurable options */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 -#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#ifdef CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 #endif /* @@ -164,54 +155,63 @@ #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_DRAM_BASE 0xa0000000 +#define CONFIG_SYS_DRAM_SIZE 0x04000000 -#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 #define FPGA_REGS_BASE_PHYSICAL 0x08000000 /* * GPIO settings */ -#define CFG_GPSR0_VAL 0x00008000 -#define CFG_GPSR1_VAL 0x00FC0382 -#define CFG_GPSR2_VAL 0x0001FFFF -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0x0060A800 -#define CFG_GPDR1_VAL 0x00FF0382 -#define CFG_GPDR2_VAL 0x0001C000 -#define CFG_GAFR0_L_VAL 0x98400000 -#define CFG_GAFR0_U_VAL 0x00002950 -#define CFG_GAFR1_L_VAL 0x000A9558 -#define CFG_GAFR1_U_VAL 0x0005AAAA -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 - -#define CFG_PSSR_VAL 0x20 +#define CONFIG_SYS_GPSR0_VAL 0x00008000 +#define CONFIG_SYS_GPSR1_VAL 0x00FC0382 +#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0x0060A800 +#define CONFIG_SYS_GPDR1_VAL 0x00FF0382 +#define CONFIG_SYS_GPDR2_VAL 0x0001C000 +#define CONFIG_SYS_GAFR0_L_VAL 0x98400000 +#define CONFIG_SYS_GAFR0_U_VAL 0x00002950 +#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558 +#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA +#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 +#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 + +#define CONFIG_SYS_PSSR_VAL 0x20 + +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 /* * Memory settings */ -#define CFG_MSC0_VAL 0x23F223F2 -#define CFG_MSC1_VAL 0x3FF1A441 -#define CFG_MSC2_VAL 0x7FF97FF1 -#define CFG_MDCNFG_VAL 0x00001AC9 -#define CFG_MDREFR_VAL 0x00018018 -#define CFG_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_MSC0_VAL 0x23F223F2 +#define CONFIG_SYS_MSC1_VAL 0x3FF1A441 +#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 +#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 +#define CONFIG_SYS_MDREFR_VAL 0x00018018 +#define CONFIG_SYS_MDMRS_VAL 0x00000000 + +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00010504 +#define CONFIG_SYS_MCMEM1_VAL 0x00010504 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00010504 +#define CONFIG_SYS_MCIO0_VAL 0x00004715 +#define CONFIG_SYS_MCIO1_VAL 0x00004715 #define _LED 0x08000010 #define LED_BLANK 0x08000040 @@ -219,21 +219,21 @@ /* * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ /* NOTE: many default partitioning schemes assume the kernel starts at the * second sector, not an environment. You have been warned! */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) +#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) /*