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drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue
authorRodrigo Vivi <rodrigo.vivi@gmail.com>
Mon, 6 May 2013 22:37:37 +0000 (19:37 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 10 May 2013 19:56:50 +0000 (21:56 +0200)
commit285541647a816e00348916ba7387eeacea30eba9
tree7fbf02d900bb2865ac6f3230a16df557a708637atree | snapshot
parent891348b2bf08d8946e0621bec49802897b28c1c4commit | diff
drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue

Display register 420B0h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | history
Linux kernel for KaRo TX COM modules