IA32-Intel Devel guide Volume 3A - 14.3.2.1
-------------------------------------------
...
Opportunistic processor performance operation can be disabled by setting bit 38 of
IA32_MISC_ENABLES. This mechanism is intended for BIOS only. If
IA32_MISC_ENABLES[38] is set, CPUID.06H:EAX[1] will return 0.
Better detect things via cpuid, this cleans up the code a bit
and the MSR parts were not working correctly anyway.
Signed-off-by: Thomas Renninger <trenn@suse.de>
CC: lenb@kernel.org
CC: linux@dominikbrodowski.net
CC: cpufreq@vger.kernel.org
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
}
cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
}
+ if (cpu_info->vendor == X86_VENDOR_INTEL) {
+ if (cpuid_level >= 6 &&
+ (cpuid_eax(6) & (1 << 1)))
+ cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA;
+ }
+
if (cpu_info->vendor == X86_VENDOR_INTEL) {
/* Intel's perf-bias MSR support */
if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3)))
if (cpu_info->vendor == X86_VENDOR_INTEL) {
/* Intel's perf-bias MSR support */
if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3)))
#define CPUPOWER_CAP_PERF_BIAS 0x00000008
#define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010
#define CPUPOWER_CAP_IS_SNB 0x00000011
#define CPUPOWER_CAP_PERF_BIAS 0x00000008
#define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010
#define CPUPOWER_CAP_IS_SNB 0x00000011
+#define CPUPOWER_CAP_INTEL_IDA 0x00000012
#define MAX_HW_PSTATES 10
#define MAX_HW_PSTATES 10
extern int msr_intel_get_perf_bias(unsigned int cpu);
extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu);
extern int msr_intel_get_perf_bias(unsigned int cpu);
extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu);
-extern int msr_intel_has_boost_support(unsigned int cpu);
-extern int msr_intel_boost_is_active(unsigned int cpu);
-
/* Read/Write msr ****************************/
/* PCI stuff ****************************/
/* Read/Write msr ****************************/
/* PCI stuff ****************************/
static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu)
{ return 0; };
static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu)
{ return 0; };
-static inline int msr_intel_has_boost_support(unsigned int cpu)
-{ return -1; };
-static inline int msr_intel_boost_is_active(unsigned int cpu)
-{ return -1; };
-
/* Read/Write msr ****************************/
static inline int cpufreq_has_boost_support(unsigned int cpu, int *support,
/* Read/Write msr ****************************/
static inline int cpufreq_has_boost_support(unsigned int cpu, int *support,
if (ret <= 0)
return ret;
*support = 1;
if (ret <= 0)
return ret;
*support = 1;
- } else if (cpupower_cpu_info.vendor == X86_VENDOR_INTEL) {
- ret = msr_intel_has_boost_support(cpu);
- if (ret <= 0)
- return ret;
- *support = ret;
- ret = msr_intel_boost_is_active(cpu);
- if (ret <= 0)
- return ret;
- *active = ret;
- }
+ } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)
+ *support = *active = 1;
return 0;
}
#endif /* #if defined(__i386__) || defined(__x86_64__) */
return 0;
}
#endif /* #if defined(__i386__) || defined(__x86_64__) */
-int msr_intel_has_boost_support(unsigned int cpu)
-{
- unsigned long long misc_enables;
- int ret;
-
- ret = read_msr(cpu, MSR_IA32_MISC_ENABLES, &misc_enables);
- if (ret)
- return ret;
-
- return (misc_enables >> 38) & 0x1;
-}
-
-int msr_intel_boost_is_active(unsigned int cpu)
-{
- unsigned long long perf_status;
- int ret;
-
- ret = read_msr(cpu, MSR_IA32_PERF_STATUS, &perf_status);
- if (ret)
- return ret;
- return (perf_status >> 32) & 0x1;
-}
-
int msr_intel_get_perf_bias(unsigned int cpu)
{
unsigned long long val;
int msr_intel_get_perf_bias(unsigned int cpu)
{
unsigned long long val;