+#define MII_MMD_ACCESS_CTRL_REG 0xd
+#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
+#define MII_DBG_PORT_REG 0x1d
+#define MII_DBG_PORT2_REG 0x1e
+
+int fecmxc_mii_postcall(int phy)
+{
+ unsigned short val;
+
+ /*
+ * Due to the i.MX6Q Armadillo2 board HW design,there is
+ * no 125Mhz clock input from SOC. In order to use RGMII,
+ * We need enable AR8031 ouput a 125MHz clk from CLK_25M
+ */
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
+ miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
+ val &= 0xffe3;
+ val |= 0x18;
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
+
+ /* For the RGMII phy, we need enable tx clock delay */
+ miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
+ miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
+ val |= 0x0100;
+ miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
+
+ miiphy_write("FEC", phy, MII_BMCR, 0xa100);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC");
+ if (!dev) {
+ printf("FEC MXC: Unable to get FEC device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXC: Unable to register FEC mii postcall\n");
+ return ret;
+ }
+
+ return 0;
+}
+