board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index 092c9ff0dcefc1c621ca1f8c6d08b7a7f8a5a6d8..9605f8b606c5e27927befe14b2b25c4ce2922ba6 100644 (file)
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -4,10 +4,15 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
 # SPDX-License-Identifier:      GPL-2.0+
 #
 

+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else

 obj-$(CONFIG_T2080RDB) += t208xrdb.o
 obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
 obj-$(CONFIG_T2080RDB) += cpld.o
 obj-$(CONFIG_PCI)      += pci.o
 obj-$(CONFIG_T2080RDB) += t208xrdb.o
 obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
 obj-$(CONFIG_T2080RDB) += cpld.o
 obj-$(CONFIG_PCI)      += pci.o

+endif
+

 obj-y   += ddr.o
 obj-y   += law.o
 obj-y   += tlb.o
 obj-y   += ddr.o
 obj-y   += law.o
 obj-y   += tlb.o

diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index 0012c6cb408dddecbe367646af636a91a79de2ce..fe26de55c09df47d5d6cc7af3820b6fb6089ca34 100644 (file)
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -120,7 +120,7 @@ Start Address   End Address Definition                      Max size
 0xEBF00000     0xEBF1FFFF      FMAN ucode (alt bank)           128KB
 0xEBE00000     0xEBE3FFFF      PHY CS4315 firmware (alt bank)  256KB
 0xE9300000     0xEBEFFFFF      rootfs (current bank)           44MB
 0xEBF00000     0xEBF1FFFF      FMAN ucode (alt bank)           128KB
 0xEBE00000     0xEBE3FFFF      PHY CS4315 firmware (alt bank)  256KB
 0xE9300000     0xEBEFFFFF      rootfs (current bank)           44MB

-0xE8800000     0xE88FFFFF      Hardware device tree (cur bank) 11MB + 512KB
+0xE8800000     0xE88FFFFF      Hardware device tree (cur bank) 1MB

 0xE8020000     0xE86FFFFF      Linux.uImage (current bank)     7MB + 875KB
 0xE8000000     0xE801FFFF      RCW (current bank)              128KB
 
 0xE8020000     0xE86FFFFF      Linux.uImage (current bank)     7MB + 875KB
 0xE8000000     0xE801FFFF      RCW (current bank)              128KB
 


@@ -146,7 +146,8 @@ Software configurations and board settings
 ------------------------------------------
 1. NOR boot:
    a. build NOR boot image
 ------------------------------------------
 1. NOR boot:
    a. build NOR boot image

-       $ make T2080RDB
+       $ make T2080RDB_config
+       $ make

    b. program u-boot.bin image to NOR flash
        => tftp 1000000 u-boot.bin
        => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
    b. program u-boot.bin image to NOR flash
        => tftp 1000000 u-boot.bin
        => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize


@@ -164,9 +165,9 @@ Software configurations and board settings
 2. NAND Boot:
    a. build PBL image for NAND boot
        $ make T2080RDB_NAND_config
 2. NAND Boot:
    a. build PBL image for NAND boot
        $ make T2080RDB_NAND_config

-       $ make u-boot.pbl
-   b. program u-boot.pbl to NAND flash
-       => tftp 1000000 u-boot.pbl
+       $ make
+   b. program u-boot-with-spl-pbl.bin to NAND flash
+       => tftp 1000000 u-boot-with-spl-pbl.bin

        => nand erase 0 d0000
        => nand write 1000000 0 $filesize
        set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
        => nand erase 0 d0000
        => nand write 1000000 0 $filesize
        set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot


@@ -174,9 +175,9 @@ Software configurations and board settings
 3. SPI Boot:
    a. build PBL image for SPI boot
        $ make T2080RDB_SPIFLASH_config
 3. SPI Boot:
    a. build PBL image for SPI boot
        $ make T2080RDB_SPIFLASH_config

-       $ make u-boot.pbl
-   b. program u-boot.pbl to SPI flash
-       => tftp 1000000 u-boot.pbl
+       $ make
+   b. program u-boot-with-spl-pbl.bin to SPI flash
+       => tftp 1000000 u-boot-with-spl-pbl.bin

        => sf probe 0
        => sf erase 0 d0000
        => sf write 1000000 0 $filesize
        => sf probe 0
        => sf erase 0 d0000
        => sf write 1000000 0 $filesize


@@ -185,13 +186,68 @@ Software configurations and board settings
 4. SD Boot:
    a. build PBL image for SD boot
        $ make T2080RDB_SDCARD_config
 4. SD Boot:
    a. build PBL image for SD boot
        $ make T2080RDB_SDCARD_config

-       $ make u-boot.pbl
-   b. program u-boot.pbl to TF card
-       => tftp 1000000 u-boot.pbl
-       => mmc write 1000000 8 1650
+       $ make
+   b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
+       => tftp 1000000 u-boot-with-spl-pbl.bin
+       => mmc write 1000000 8 0x800

        set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
 
 
        set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
 
 

+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area             | Address                    |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB)         |
+-------------------------------------------------
+|GD, BD                   | 0xFFFC8000 (4KB)           |
+-------------------------------------------------
+|ENV              | 0xFFFC9000 (8KB)           |
+-------------------------------------------------
+|HEAP             | 0xFFFCB000 (50KB)          |
+-------------------------------------------------
+|STACK            | 0xFFFD8000 (22KB)          |
+-------------------------------------------------
+|U-boot SPL       | 0xFFFD8000 (160KB)         |
+-------------------------------------------------
+
+NAND Flash memory Map on T2080RDB
+--------------------------------------------------------------
+Start          End             Definition      Size
+0x000000       0x0FFFFF        u-boot img      1MB  (2 blocks)
+0x100000       0x17FFFF        u-boot env      512KB (1 block)
+0x180000       0x1FFFFF        FMAN ucode      512KB (1 block)
+0x200000       0x27FFFF        CS4315 ucode    512KB (1 block)
+
+
+Micro SD Card memory Map on T2080RDB
+----------------------------------------------------
+Block          #blocks         Definition      Size
+0x008          2048            u-boot img      1MB
+0x800          0016            u-boot env      8KB
+0x820          0128            FMAN ucode      64KB
+0x8a0          0512            CS4315 ucode    256KB
+
+
+SPI Flash memory Map on T2080RDB
+----------------------------------------------------
+Start          End             Definition      Size
+0x000000       0x0FFFFF        u-boot img      1MB
+0x100000       0x101FFF        u-boot env      8KB
+0x110000       0x11FFFF        FMAN ucode      64KB
+0x120000        0x15FFFF        CS4315 ucode   256KB
+
+

 How to update the ucode of Cortina CS4315/CS4340 10G PHY
 --------------------------------------------------------
 => tftp 1000000 CS4315-CS4340-PHY-ucode.txt
 How to update the ucode of Cortina CS4315/CS4340 10G PHY
 --------------------------------------------------------
 => tftp 1000000 CS4315-CS4340-PHY-ucode.txt

diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 01e917398f93372be22be2246dd07a9aa0ee1166..8a26276273566fff4268950bc76cdba930eafe20 100644 (file)
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -100,13 +100,15 @@ phys_size_t initdram(int board_type)
 {
        phys_size_t dram_size;
 
 {
        phys_size_t dram_size;
 

+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)

        puts("Initializing....using SPD\n");
        puts("Initializing....using SPD\n");

-

        dram_size = fsl_ddr_sdram();
 
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;
        dram_size = fsl_ddr_sdram();
 
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;

-
-       puts("    DDR: ");
+#else
+       /* DDR has been initialised by first stage boot loader */
+       dram_size = fsl_ddr_sdram_size();
+#endif

        return dram_size;
 }
        return dram_size;
 }

diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
new file mode 100644 (file)
index 0000000..9ae2b1e
--- /dev/null
+++ b/board/freescale/t208xrdb/spl.c
@@ -0,0 +1,107 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+       return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+       return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+       return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+       u32 plat_ratio, sys_clk, ccb_clk;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+       /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+       memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+       /* Update GD pointer */
+       gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+       console_init_f();
+
+       /* initialize selected port with appropriate baud rate */
+       sys_clk = get_board_sys_clk();
+       plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+       ccb_clk = sys_clk * plat_ratio / 2;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                    ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+       puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+       puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+       puts("\nNAND boot...\n");
+#endif
+
+       relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       bd_t *bd;
+
+       bd = (bd_t *)(gd + sizeof(gd_t));
+       memset(bd, 0, sizeof(bd_t));
+       gd->bd = bd;
+       bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+       bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+       probecpu();
+       get_clocks();
+       mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+                       CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+       nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                           (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_initialize(bd);
+       mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                          (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+       spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                          (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+       gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+       gd->env_valid = 1;
+
+       i2c_init_all();
+
+       gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+       spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+       nand_boot();
+#endif
+}

diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 085d9f5c6a9c591e0327b4798b40dddd475a5928..2ebea36a5c22d5664c3fea4129f347bb8b6bc2af 100644 (file)
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),
 
                      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),
 

+#ifndef CONFIG_SPL_BUILD

        /* *I*G* - PCIe 1, 0x80000000 */
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
        /* *I*G* - PCIe 1, 0x80000000 */
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


@@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif

+#endif

 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


@@ -140,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
                      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
                      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif

-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)

        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 19, BOOKE_PAGESZ_2G, 1)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 19, BOOKE_PAGESZ_2G, 1)

diff --git a/boards.cfg b/boards.cfg
index 92ad1e50cfd0291cba58e6615c776f5ecd47a822..7f91210f6f19b15af3c04f2f671d433d09bb1a9e 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -965,9 +965,9 @@ Active  powerpc     mpc85xx        -           freescale       t208xqds
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB                             T208xRDB:PPC_T2080                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB                             T208xRDB:PPC_T2080                                                                                                                -

-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD                      T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH                    T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD                      T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH                    T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH

 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SRIO_PCIE_BOOT              T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SECURE_BOOT                 T4240QDS:PPC_T4160,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SRIO_PCIE_BOOT              T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SECURE_BOOT                 T4240QDS:PPC_T4160,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 5c89426bde6b946137c2cdf0c45cfcd094ccec03..4ef1167f9f5e63a7d38a35e32e00bbc117cd05e6 100644 (file)
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -39,12 +39,76 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_RAMBOOT_PBL

-#define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc

 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg

+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE           0x00201000
+#define CONFIG_SPL_TEXT_BASE           0xFFFD8000
+#define CONFIG_SPL_PAD_TO              0x40000
+#define CONFIG_SPL_MAX_SIZE            0x28000
+#define RESET_VECTOR_OFFSET            0x27FFC
+#define BOOT_PAGE_OFFSET               0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST     0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 << 10)
+#define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT

 #endif
 
 #endif
 

+#endif /* CONFIG_RAMBOOT_PBL */
+

 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */


@@ -74,11 +138,7 @@
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 

-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
+#ifndef CONFIG_SYS_NO_FLASH

 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE


@@ -99,11 +159,11 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #define CONFIG_ENV_SIZE                0x2000

-#define CONFIG_ENV_OFFSET      (512 * 1658)
+#define CONFIG_ENV_OFFSET      (512 * 0x800)

 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND

-#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE                0x2000

 #define CONFIG_ENV_OFFSET      (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_OFFSET      (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE


@@ -129,7 +189,16 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Config the L3 Cache as L3 SRAM
  */
 /*
  * Config the L3 Cache as L3 SRAM
  */

-#define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR                0xFFFC0000
+#define CONFIG_SYS_L3_SIZE             (512 << 10)
+#define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR                        (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE   (50 << 10)
+#define CONFIG_SPL_RELOC_STACK         (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE    (22 << 10)

 
 #define CONFIG_SYS_DCSRBAR     0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS        0xf00000000ull
 
 #define CONFIG_SYS_DCSRBAR     0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS        0xf00000000ull


@@ -301,7 +370,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_SYS_RAMBOOT
 #endif
 

-#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+

 #define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
 #define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG


@@ -516,17 +590,17 @@ unsigned long get_board_ddr_clk(void);
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is

- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.

  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC

-#define CONFIG_SYS_FMAN_FW_ADDR        (512 * 1680)
-#define CONFIG_CORTINA_FW_ADDR         (512 * 1808)
+#define CONFIG_SYS_FMAN_FW_ADDR                (512 * 0x820)
+#define CONFIG_CORTINA_FW_ADDR         (512 * 0x8a0)

 
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND

-#define CONFIG_SYS_FMAN_FW_ADDR        (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_CORTINA_FW_ADDR         (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR                (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR         (4 * CONFIG_SYS_NAND_BLOCK_SIZE)

 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing