Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
#endif /* __MIGO_R_H */
#define CONFIG_SYS_HZ 1000
#endif /* __MIGO_R_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
#endif /* __AP325RXA_H */
#define CONFIG_SYS_HZ 1000
#endif /* __AP325RXA_H */
/* Clocks */
#define CONFIG_SYS_CLK_FREQ 24000000
/* Clocks */
#define CONFIG_SYS_CLK_FREQ 24000000
-#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
/* UART */
#define CONFIG_SYS_HZ 1000
/* UART */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
/* PCMCIA */
#define CONFIG_SYS_HZ 1000
/* PCMCIA */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
#endif /* __MS7722SE_H */
#define CONFIG_SYS_HZ 1000
#endif /* __MS7722SE_H */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER 4
+#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __MS7750SE_H */
#define CONFIG_SYS_HZ 1000
#endif /* __MS7750SE_H */
* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
* SuperH Clock setting
*/
#define CONFIG_SYS_CLK_FREQ 60000000
-#define TMU_CLK_DIVIDER 4
+#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define TMU_CLK_DIVIDER 4
+#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
/* PCI Controller */
#define CONFIG_SYS_HZ 1000
/* PCI Controller */
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
/* Clock */
#define CONFIG_SYS_CLK_FREQ 66666666
-#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_SYS_HZ 1000
/* Ether */
#define CONFIG_SYS_HZ 1000
/* Ether */
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ 50000000
-#define TMU_CLK_DIVIDER 4
+#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __SH7785LCR_H */
#define CONFIG_SYS_HZ 1000
#endif /* __SH7785LCR_H */
- /* Divide clock by TMU_CLK_DIVIDER */
+ /* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
- switch (TMU_CLK_DIVIDER) {
+ switch (CONFIG_SYS_TMU_CLK_DIV) {
case 1024:
bit = 4;
break;
case 1024:
bit = 4;
break;