+#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
+
+/* PSS */
+#ifdef KS2_NETCP_V1_0
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
+#define hw_config_streaming_switch()\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
+
+#elif defined KS2_NETCP_V1_5
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
+
+#define hw_config_streaming_switch()\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+4);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+8);\
+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+ DEVICE_PSTREAM_CFG_REG_ADDR+12);
+
+#endif